Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010 |
| 4 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 8 | * Designware ethernet IP driver for U-Boot |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 12 | #include <clk.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 13 | #include <cpu_func.h> |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 14 | #include <dm.h> |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 15 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 16 | #include <log.h> |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 17 | #include <miiphy.h> |
| 18 | #include <malloc.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 19 | #include <net.h> |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 20 | #include <pci.h> |
Ley Foon Tan | 27d5c00 | 2018-06-14 18:45:23 +0800 | [diff] [blame] | 21 | #include <reset.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 22 | #include <asm/cache.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 23 | #include <dm/device_compat.h> |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 24 | #include <dm/device-internal.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 25 | #include <dm/devres.h> |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 26 | #include <dm/lists.h> |
Stefan Roese | d27e86c | 2012-05-07 12:04:25 +0200 | [diff] [blame] | 27 | #include <linux/compiler.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 28 | #include <linux/delay.h> |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 29 | #include <linux/err.h> |
Florian Fainelli | 65f686b | 2017-12-09 14:59:55 -0800 | [diff] [blame] | 30 | #include <linux/kernel.h> |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 31 | #include <asm/io.h> |
Jacob Chen | 7ceacea | 2017-03-27 16:54:17 +0800 | [diff] [blame] | 32 | #include <power/regulator.h> |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 33 | #include "designware.h" |
| 34 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 35 | static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
| 36 | { |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 37 | #ifdef CONFIG_DM_ETH |
| 38 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); |
| 39 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 40 | #else |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 41 | struct eth_mac_regs *mac_p = bus->priv; |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 42 | #endif |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 43 | ulong start; |
| 44 | u16 miiaddr; |
| 45 | int timeout = CONFIG_MDIO_TIMEOUT; |
| 46 | |
| 47 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | |
| 48 | ((reg << MIIREGSHIFT) & MII_REGMSK); |
| 49 | |
| 50 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); |
| 51 | |
| 52 | start = get_timer(0); |
| 53 | while (get_timer(start) < timeout) { |
| 54 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) |
| 55 | return readl(&mac_p->miidata); |
| 56 | udelay(10); |
| 57 | }; |
| 58 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 59 | return -ETIMEDOUT; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
| 63 | u16 val) |
| 64 | { |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 65 | #ifdef CONFIG_DM_ETH |
| 66 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); |
| 67 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 68 | #else |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 69 | struct eth_mac_regs *mac_p = bus->priv; |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 70 | #endif |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 71 | ulong start; |
| 72 | u16 miiaddr; |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 73 | int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 74 | |
| 75 | writel(val, &mac_p->miidata); |
| 76 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | |
| 77 | ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; |
| 78 | |
| 79 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); |
| 80 | |
| 81 | start = get_timer(0); |
| 82 | while (get_timer(start) < timeout) { |
| 83 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { |
| 84 | ret = 0; |
| 85 | break; |
| 86 | } |
| 87 | udelay(10); |
| 88 | }; |
| 89 | |
| 90 | return ret; |
| 91 | } |
| 92 | |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 93 | #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) |
Neil Armstrong | 1188a6d | 2021-04-21 10:58:01 +0200 | [diff] [blame] | 94 | static int __dw_mdio_reset(struct udevice *dev) |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 95 | { |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 96 | struct dw_eth_dev *priv = dev_get_priv(dev); |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 97 | struct dw_eth_pdata *pdata = dev_get_plat(dev); |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 98 | int ret; |
| 99 | |
| 100 | if (!dm_gpio_is_valid(&priv->reset_gpio)) |
| 101 | return 0; |
| 102 | |
| 103 | /* reset the phy */ |
| 104 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); |
| 105 | if (ret) |
| 106 | return ret; |
| 107 | |
| 108 | udelay(pdata->reset_delays[0]); |
| 109 | |
| 110 | ret = dm_gpio_set_value(&priv->reset_gpio, 1); |
| 111 | if (ret) |
| 112 | return ret; |
| 113 | |
| 114 | udelay(pdata->reset_delays[1]); |
| 115 | |
| 116 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); |
| 117 | if (ret) |
| 118 | return ret; |
| 119 | |
| 120 | udelay(pdata->reset_delays[2]); |
| 121 | |
| 122 | return 0; |
| 123 | } |
Neil Armstrong | 1188a6d | 2021-04-21 10:58:01 +0200 | [diff] [blame] | 124 | |
| 125 | static int dw_mdio_reset(struct mii_dev *bus) |
| 126 | { |
| 127 | struct udevice *dev = bus->priv; |
| 128 | |
| 129 | return __dw_mdio_reset(dev); |
| 130 | } |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 131 | #endif |
| 132 | |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 133 | #if IS_ENABLED(CONFIG_DM_MDIO) |
| 134 | int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg) |
| 135 | { |
| 136 | struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); |
| 137 | |
| 138 | return dw_mdio_read(pdata->mii_bus, addr, devad, reg); |
| 139 | } |
| 140 | |
| 141 | int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) |
| 142 | { |
| 143 | struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev); |
| 144 | |
| 145 | return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val); |
| 146 | } |
| 147 | |
| 148 | #if CONFIG_IS_ENABLED(DM_GPIO) |
| 149 | int designware_eth_mdio_reset(struct udevice *mdio_dev) |
| 150 | { |
Neil Armstrong | 1188a6d | 2021-04-21 10:58:01 +0200 | [diff] [blame] | 151 | struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev); |
| 152 | struct udevice *dev = mdio_pdata->mii_bus->priv; |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 153 | |
Neil Armstrong | 1188a6d | 2021-04-21 10:58:01 +0200 | [diff] [blame] | 154 | return __dw_mdio_reset(dev->parent); |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 155 | } |
| 156 | #endif |
| 157 | |
| 158 | static const struct mdio_ops designware_eth_mdio_ops = { |
| 159 | .read = designware_eth_mdio_read, |
| 160 | .write = designware_eth_mdio_write, |
| 161 | #if CONFIG_IS_ENABLED(DM_GPIO) |
| 162 | .reset = designware_eth_mdio_reset, |
| 163 | #endif |
| 164 | }; |
| 165 | |
| 166 | static int designware_eth_mdio_probe(struct udevice *dev) |
| 167 | { |
| 168 | /* Use the priv data of parent */ |
| 169 | dev_set_priv(dev, dev_get_priv(dev->parent)); |
| 170 | |
| 171 | return 0; |
| 172 | } |
| 173 | |
| 174 | U_BOOT_DRIVER(designware_eth_mdio) = { |
| 175 | .name = "eth_designware_mdio", |
| 176 | .id = UCLASS_MDIO, |
| 177 | .probe = designware_eth_mdio_probe, |
| 178 | .ops = &designware_eth_mdio_ops, |
| 179 | .plat_auto = sizeof(struct mdio_perdev_priv), |
| 180 | }; |
| 181 | #endif |
| 182 | |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 183 | static int dw_mdio_init(const char *name, void *priv) |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 184 | { |
| 185 | struct mii_dev *bus = mdio_alloc(); |
| 186 | |
| 187 | if (!bus) { |
| 188 | printf("Failed to allocate MDIO bus\n"); |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 189 | return -ENOMEM; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | bus->read = dw_mdio_read; |
| 193 | bus->write = dw_mdio_write; |
Ben Whitten | 34fd6c9 | 2015-12-30 13:05:58 +0000 | [diff] [blame] | 194 | snprintf(bus->name, sizeof(bus->name), "%s", name); |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 195 | #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 196 | bus->reset = dw_mdio_reset; |
| 197 | #endif |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 198 | |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 199 | bus->priv = priv; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 200 | |
| 201 | return mdio_register(bus); |
| 202 | } |
Vipin Kumar | b6c5999 | 2012-03-26 00:09:56 +0000 | [diff] [blame] | 203 | |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 204 | #if IS_ENABLED(CONFIG_DM_MDIO) |
| 205 | static int dw_dm_mdio_init(const char *name, void *priv) |
| 206 | { |
| 207 | struct udevice *dev = priv; |
| 208 | ofnode node; |
| 209 | int ret; |
| 210 | |
| 211 | ofnode_for_each_subnode(node, dev_ofnode(dev)) { |
| 212 | const char *subnode_name = ofnode_get_name(node); |
| 213 | struct udevice *mdiodev; |
| 214 | |
| 215 | if (strcmp(subnode_name, "mdio")) |
| 216 | continue; |
| 217 | |
| 218 | ret = device_bind_driver_to_node(dev, "eth_designware_mdio", |
| 219 | subnode_name, node, &mdiodev); |
| 220 | if (ret) |
| 221 | debug("%s: not able to bind mdio device node\n", __func__); |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | printf("%s: mdio node is missing, registering legacy mdio bus", __func__); |
| 227 | |
| 228 | return dw_mdio_init(name, priv); |
| 229 | } |
| 230 | #endif |
| 231 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 232 | static void tx_descs_init(struct dw_eth_dev *priv) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 233 | { |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 234 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
| 235 | struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; |
| 236 | char *txbuffs = &priv->txbuffs[0]; |
| 237 | struct dmamacdescr *desc_p; |
| 238 | u32 idx; |
| 239 | |
| 240 | for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { |
| 241 | desc_p = &desc_table_p[idx]; |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 242 | desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; |
| 243 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 244 | |
| 245 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
| 246 | desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | |
Marek Vasut | 4ab539a | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 247 | DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | |
| 248 | DESC_TXSTS_TXCHECKINSCTRL | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 249 | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); |
| 250 | |
| 251 | desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; |
| 252 | desc_p->dmamac_cntl = 0; |
| 253 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); |
| 254 | #else |
| 255 | desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; |
| 256 | desc_p->txrx_status = 0; |
| 257 | #endif |
| 258 | } |
| 259 | |
| 260 | /* Correcting the last pointer of the chain */ |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 261 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 262 | |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 263 | /* Flush all Tx buffer descriptors at once */ |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 264 | flush_dcache_range((ulong)priv->tx_mac_descrtable, |
| 265 | (ulong)priv->tx_mac_descrtable + |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 266 | sizeof(priv->tx_mac_descrtable)); |
| 267 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 268 | writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); |
Alexey Brodkin | 4695ddd | 2014-01-13 13:28:38 +0400 | [diff] [blame] | 269 | priv->tx_currdescnum = 0; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 270 | } |
| 271 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 272 | static void rx_descs_init(struct dw_eth_dev *priv) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 273 | { |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 274 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
| 275 | struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; |
| 276 | char *rxbuffs = &priv->rxbuffs[0]; |
| 277 | struct dmamacdescr *desc_p; |
| 278 | u32 idx; |
| 279 | |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 280 | /* Before passing buffers to GMAC we need to make sure zeros |
| 281 | * written there right after "priv" structure allocation were |
| 282 | * flushed into RAM. |
| 283 | * Otherwise there's a chance to get some of them flushed in RAM when |
| 284 | * GMAC is already pushing data to RAM via DMA. This way incoming from |
| 285 | * GMAC data will be corrupted. */ |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 286 | flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 287 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 288 | for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { |
| 289 | desc_p = &desc_table_p[idx]; |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 290 | desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; |
| 291 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 292 | |
| 293 | desc_p->dmamac_cntl = |
Marek Vasut | 4ab539a | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 294 | (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 295 | DESC_RXCTRL_RXCHAIN; |
| 296 | |
| 297 | desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; |
| 298 | } |
| 299 | |
| 300 | /* Correcting the last pointer of the chain */ |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 301 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 302 | |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 303 | /* Flush all Rx buffer descriptors at once */ |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 304 | flush_dcache_range((ulong)priv->rx_mac_descrtable, |
| 305 | (ulong)priv->rx_mac_descrtable + |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 306 | sizeof(priv->rx_mac_descrtable)); |
| 307 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 308 | writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); |
Alexey Brodkin | 4695ddd | 2014-01-13 13:28:38 +0400 | [diff] [blame] | 309 | priv->rx_currdescnum = 0; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 310 | } |
| 311 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 312 | static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 313 | { |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 314 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 315 | u32 macid_lo, macid_hi; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 316 | |
| 317 | macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + |
| 318 | (mac_id[3] << 24); |
| 319 | macid_hi = mac_id[4] + (mac_id[5] << 8); |
| 320 | |
| 321 | writel(macid_hi, &mac_p->macaddr0hi); |
| 322 | writel(macid_lo, &mac_p->macaddr0lo); |
| 323 | |
| 324 | return 0; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 325 | } |
| 326 | |
Simon Glass | 4afa85e | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 327 | static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, |
| 328 | struct phy_device *phydev) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 329 | { |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 330 | u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 331 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 332 | if (!phydev->link) { |
| 333 | printf("%s: No link.\n", phydev->dev->name); |
Simon Glass | 4afa85e | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 334 | return 0; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 335 | } |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 336 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 337 | if (phydev->speed != 1000) |
| 338 | conf |= MII_PORTSELECT; |
Alexey Brodkin | a5e8819 | 2016-01-13 16:59:36 +0300 | [diff] [blame] | 339 | else |
| 340 | conf &= ~MII_PORTSELECT; |
Vipin Kumar | f567e41 | 2012-12-13 17:22:51 +0530 | [diff] [blame] | 341 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 342 | if (phydev->speed == 100) |
| 343 | conf |= FES_100; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 344 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 345 | if (phydev->duplex) |
| 346 | conf |= FULLDPLXMODE; |
Amit Virdi | 470e884 | 2012-03-26 00:09:59 +0000 | [diff] [blame] | 347 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 348 | writel(conf, &mac_p->conf); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 349 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 350 | printf("Speed: %d, %s duplex%s\n", phydev->speed, |
| 351 | (phydev->duplex) ? "full" : "half", |
| 352 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); |
Simon Glass | 4afa85e | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 353 | |
| 354 | return 0; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 355 | } |
| 356 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 357 | static void _dw_eth_halt(struct dw_eth_dev *priv) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 358 | { |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 359 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 360 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 361 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 362 | writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); |
| 363 | writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 364 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 365 | phy_shutdown(priv->phydev); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 366 | } |
| 367 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 368 | int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 369 | { |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 370 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 371 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 372 | unsigned int start; |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 373 | int ret; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 374 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 375 | writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); |
Vipin Kumar | b6c5999 | 2012-03-26 00:09:56 +0000 | [diff] [blame] | 376 | |
Quentin Schulz | 7f920dd | 2018-06-04 12:17:33 +0200 | [diff] [blame] | 377 | /* |
| 378 | * When a MII PHY is used, we must set the PS bit for the DMA |
| 379 | * reset to succeed. |
| 380 | */ |
| 381 | if (priv->phydev->interface == PHY_INTERFACE_MODE_MII) |
| 382 | writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf); |
| 383 | else |
| 384 | writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf); |
| 385 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 386 | start = get_timer(0); |
| 387 | while (readl(&dma_p->busmode) & DMAMAC_SRST) { |
Alexey Brodkin | 71eccc3 | 2015-01-13 17:10:24 +0300 | [diff] [blame] | 388 | if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { |
| 389 | printf("DMA reset timeout\n"); |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 390 | return -ETIMEDOUT; |
Alexey Brodkin | 71eccc3 | 2015-01-13 17:10:24 +0300 | [diff] [blame] | 391 | } |
Stefan Roese | d27e86c | 2012-05-07 12:04:25 +0200 | [diff] [blame] | 392 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 393 | mdelay(100); |
| 394 | }; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 395 | |
Bin Meng | 2ddfa2a | 2015-06-15 18:40:19 +0800 | [diff] [blame] | 396 | /* |
| 397 | * Soft reset above clears HW address registers. |
| 398 | * So we have to set it here once again. |
| 399 | */ |
| 400 | _dw_write_hwaddr(priv, enetaddr); |
| 401 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 402 | rx_descs_init(priv); |
| 403 | tx_descs_init(priv); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 404 | |
Ian Campbell | 4164b74 | 2014-05-08 22:26:35 +0100 | [diff] [blame] | 405 | writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 406 | |
Sonic Zhang | b917b62 | 2015-01-29 14:38:50 +0800 | [diff] [blame] | 407 | #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 408 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, |
| 409 | &dma_p->opmode); |
Sonic Zhang | b917b62 | 2015-01-29 14:38:50 +0800 | [diff] [blame] | 410 | #else |
| 411 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO, |
| 412 | &dma_p->opmode); |
| 413 | #endif |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 414 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 415 | writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); |
Vipin Kumar | 7443d60 | 2012-05-07 13:06:44 +0530 | [diff] [blame] | 416 | |
Sonic Zhang | 962c95c | 2015-01-29 13:37:31 +0800 | [diff] [blame] | 417 | #ifdef CONFIG_DW_AXI_BURST_LEN |
| 418 | writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); |
| 419 | #endif |
| 420 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 421 | /* Start up the PHY */ |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 422 | ret = phy_startup(priv->phydev); |
| 423 | if (ret) { |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 424 | printf("Could not initialize PHY %s\n", |
| 425 | priv->phydev->dev->name); |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 426 | return ret; |
Vipin Kumar | 7443d60 | 2012-05-07 13:06:44 +0530 | [diff] [blame] | 427 | } |
| 428 | |
Simon Glass | 4afa85e | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 429 | ret = dw_adjust_link(priv, mac_p, priv->phydev); |
| 430 | if (ret) |
| 431 | return ret; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 432 | |
Simon Glass | 3240e94 | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 433 | return 0; |
| 434 | } |
| 435 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 436 | int designware_eth_enable(struct dw_eth_dev *priv) |
Simon Glass | 3240e94 | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 437 | { |
| 438 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 439 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 440 | if (!priv->phydev->link) |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 441 | return -EIO; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 442 | |
Armando Visconti | 038c9d5 | 2012-03-26 00:09:55 +0000 | [diff] [blame] | 443 | writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
Florian Fainelli | 65f686b | 2017-12-09 14:59:55 -0800 | [diff] [blame] | 448 | #define ETH_ZLEN 60 |
| 449 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 450 | static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 451 | { |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 452 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
| 453 | u32 desc_num = priv->tx_currdescnum; |
| 454 | struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 455 | ulong desc_start = (ulong)desc_p; |
| 456 | ulong desc_end = desc_start + |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 457 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 458 | ulong data_start = desc_p->dmamac_addr; |
| 459 | ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
Ian Campbell | 0e690fd | 2014-05-08 22:26:33 +0100 | [diff] [blame] | 460 | /* |
| 461 | * Strictly we only need to invalidate the "txrx_status" field |
| 462 | * for the following check, but on some platforms we cannot |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 463 | * invalidate only 4 bytes, so we flush the entire descriptor, |
| 464 | * which is 16 bytes in total. This is safe because the |
| 465 | * individual descriptors in the array are each aligned to |
| 466 | * ARCH_DMA_MINALIGN and padded appropriately. |
Ian Campbell | 0e690fd | 2014-05-08 22:26:33 +0100 | [diff] [blame] | 467 | */ |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 468 | invalidate_dcache_range(desc_start, desc_end); |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 469 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 470 | /* Check if the descriptor is owned by CPU */ |
| 471 | if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { |
| 472 | printf("CPU not owner of tx frame\n"); |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 473 | return -EPERM; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 474 | } |
| 475 | |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 476 | memcpy((void *)data_start, packet, length); |
Simon Goldschmidt | 80385de | 2018-11-17 10:24:42 +0100 | [diff] [blame] | 477 | if (length < ETH_ZLEN) { |
| 478 | memset(&((char *)data_start)[length], 0, ETH_ZLEN - length); |
| 479 | length = ETH_ZLEN; |
| 480 | } |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 481 | |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 482 | /* Flush data to be sent */ |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 483 | flush_dcache_range(data_start, data_end); |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 484 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 485 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
| 486 | desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; |
Simon Goldschmidt | e2d0a7c | 2018-11-17 10:24:41 +0100 | [diff] [blame] | 487 | desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) | |
| 488 | ((length << DESC_TXCTRL_SIZE1SHFT) & |
| 489 | DESC_TXCTRL_SIZE1MASK); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 490 | |
| 491 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK); |
| 492 | desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; |
| 493 | #else |
Simon Goldschmidt | e2d0a7c | 2018-11-17 10:24:41 +0100 | [diff] [blame] | 494 | desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) | |
| 495 | ((length << DESC_TXCTRL_SIZE1SHFT) & |
| 496 | DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | |
| 497 | DESC_TXCTRL_TXFIRST; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 498 | |
| 499 | desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; |
| 500 | #endif |
| 501 | |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 502 | /* Flush modified buffer descriptor */ |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 503 | flush_dcache_range(desc_start, desc_end); |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 504 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 505 | /* Test the wrap-around condition. */ |
| 506 | if (++desc_num >= CONFIG_TX_DESCR_NUM) |
| 507 | desc_num = 0; |
| 508 | |
| 509 | priv->tx_currdescnum = desc_num; |
| 510 | |
| 511 | /* Start the transmission */ |
| 512 | writel(POLL_DATA, &dma_p->txpolldemand); |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 517 | static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 518 | { |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 519 | u32 status, desc_num = priv->rx_currdescnum; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 520 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 521 | int length = -EAGAIN; |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 522 | ulong desc_start = (ulong)desc_p; |
| 523 | ulong desc_end = desc_start + |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 524 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 525 | ulong data_start = desc_p->dmamac_addr; |
| 526 | ulong data_end; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 527 | |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 528 | /* Invalidate entire buffer descriptor */ |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 529 | invalidate_dcache_range(desc_start, desc_end); |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 530 | |
| 531 | status = desc_p->txrx_status; |
| 532 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 533 | /* Check if the owner is the CPU */ |
| 534 | if (!(status & DESC_RXSTS_OWNBYDMA)) { |
| 535 | |
Marek Vasut | 4ab539a | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 536 | length = (status & DESC_RXSTS_FRMLENMSK) >> |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 537 | DESC_RXSTS_FRMLENSHFT; |
| 538 | |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 539 | /* Invalidate received data */ |
Marek Vasut | 1519304 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 540 | data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
| 541 | invalidate_dcache_range(data_start, data_end); |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 542 | *packetp = (uchar *)(ulong)desc_p->dmamac_addr; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 543 | } |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 544 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 545 | return length; |
| 546 | } |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 547 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 548 | static int _dw_free_pkt(struct dw_eth_dev *priv) |
| 549 | { |
| 550 | u32 desc_num = priv->rx_currdescnum; |
| 551 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 552 | ulong desc_start = (ulong)desc_p; |
| 553 | ulong desc_end = desc_start + |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 554 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 555 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 556 | /* |
| 557 | * Make the current descriptor valid again and go to |
| 558 | * the next one |
| 559 | */ |
| 560 | desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; |
Alexey Brodkin | 0d3b22e | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 561 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 562 | /* Flush only status field - others weren't changed */ |
| 563 | flush_dcache_range(desc_start, desc_end); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 564 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 565 | /* Test the wrap-around condition. */ |
| 566 | if (++desc_num >= CONFIG_RX_DESCR_NUM) |
| 567 | desc_num = 0; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 568 | priv->rx_currdescnum = desc_num; |
| 569 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 570 | return 0; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 571 | } |
| 572 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 573 | static int dw_phy_init(struct dw_eth_dev *priv, void *dev) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 574 | { |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 575 | struct phy_device *phydev; |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 576 | int ret; |
| 577 | |
| 578 | #if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH) |
| 579 | phydev = dm_eth_phy_connect(dev); |
| 580 | if (!phydev) |
| 581 | return -ENODEV; |
| 582 | #else |
| 583 | int phy_addr = -1; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 584 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 585 | #ifdef CONFIG_PHY_ADDR |
Simon Goldschmidt | e1922c7 | 2019-07-15 21:53:05 +0200 | [diff] [blame] | 586 | phy_addr = CONFIG_PHY_ADDR; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 587 | #endif |
| 588 | |
Simon Goldschmidt | e1922c7 | 2019-07-15 21:53:05 +0200 | [diff] [blame] | 589 | phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface); |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 590 | if (!phydev) |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 591 | return -ENODEV; |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 592 | #endif |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 593 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 594 | phydev->supported &= PHY_GBIT_FEATURES; |
Alexey Brodkin | a3d3874 | 2016-01-13 16:59:37 +0300 | [diff] [blame] | 595 | if (priv->max_speed) { |
| 596 | ret = phy_set_supported(phydev, priv->max_speed); |
| 597 | if (ret) |
| 598 | return ret; |
| 599 | } |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 600 | phydev->advertising = phydev->supported; |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 601 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 602 | priv->phydev = phydev; |
| 603 | phy_config(phydev); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 604 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 605 | return 0; |
| 606 | } |
| 607 | |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 608 | #ifndef CONFIG_DM_ETH |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 609 | static int dw_eth_init(struct eth_device *dev, struct bd_info *bis) |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 610 | { |
Simon Glass | 3240e94 | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 611 | int ret; |
| 612 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 613 | ret = designware_eth_init(dev->priv, dev->enetaddr); |
Simon Glass | 3240e94 | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 614 | if (!ret) |
| 615 | ret = designware_eth_enable(dev->priv); |
| 616 | |
| 617 | return ret; |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | static int dw_eth_send(struct eth_device *dev, void *packet, int length) |
| 621 | { |
| 622 | return _dw_eth_send(dev->priv, packet, length); |
| 623 | } |
| 624 | |
| 625 | static int dw_eth_recv(struct eth_device *dev) |
| 626 | { |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 627 | uchar *packet; |
| 628 | int length; |
| 629 | |
| 630 | length = _dw_eth_recv(dev->priv, &packet); |
| 631 | if (length == -EAGAIN) |
| 632 | return 0; |
| 633 | net_process_received_packet(packet, length); |
| 634 | |
| 635 | _dw_free_pkt(dev->priv); |
| 636 | |
| 637 | return 0; |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | static void dw_eth_halt(struct eth_device *dev) |
| 641 | { |
| 642 | return _dw_eth_halt(dev->priv); |
| 643 | } |
| 644 | |
| 645 | static int dw_write_hwaddr(struct eth_device *dev) |
| 646 | { |
| 647 | return _dw_write_hwaddr(dev->priv, dev->enetaddr); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 648 | } |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 649 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 650 | int designware_initialize(ulong base_addr, u32 interface) |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 651 | { |
| 652 | struct eth_device *dev; |
| 653 | struct dw_eth_dev *priv; |
| 654 | |
| 655 | dev = (struct eth_device *) malloc(sizeof(struct eth_device)); |
| 656 | if (!dev) |
| 657 | return -ENOMEM; |
| 658 | |
| 659 | /* |
| 660 | * Since the priv structure contains the descriptors which need a strict |
| 661 | * buswidth alignment, memalign is used to allocate memory |
| 662 | */ |
Ian Campbell | 07c92fc | 2014-05-08 22:26:32 +0100 | [diff] [blame] | 663 | priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, |
| 664 | sizeof(struct dw_eth_dev)); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 665 | if (!priv) { |
| 666 | free(dev); |
| 667 | return -ENOMEM; |
| 668 | } |
| 669 | |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 670 | if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { |
| 671 | printf("designware: buffers are outside DMA memory\n"); |
| 672 | return -EINVAL; |
| 673 | } |
| 674 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 675 | memset(dev, 0, sizeof(struct eth_device)); |
| 676 | memset(priv, 0, sizeof(struct dw_eth_dev)); |
| 677 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 678 | sprintf(dev->name, "dwmac.%lx", base_addr); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 679 | dev->iobase = (int)base_addr; |
| 680 | dev->priv = priv; |
| 681 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 682 | priv->dev = dev; |
| 683 | priv->mac_regs_p = (struct eth_mac_regs *)base_addr; |
| 684 | priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + |
| 685 | DW_DMA_BASE_OFFSET); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 686 | |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 687 | dev->init = dw_eth_init; |
| 688 | dev->send = dw_eth_send; |
| 689 | dev->recv = dw_eth_recv; |
| 690 | dev->halt = dw_eth_halt; |
| 691 | dev->write_hwaddr = dw_write_hwaddr; |
| 692 | |
| 693 | eth_register(dev); |
| 694 | |
Alexey Brodkin | 9a0b130 | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 695 | priv->interface = interface; |
| 696 | |
| 697 | dw_mdio_init(dev->name, priv->mac_regs_p); |
| 698 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 699 | |
Simon Glass | e50c4d1 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 700 | return dw_phy_init(priv, dev); |
Vipin KUMAR | 1f87312 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 701 | } |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 702 | #endif |
| 703 | |
| 704 | #ifdef CONFIG_DM_ETH |
| 705 | static int designware_eth_start(struct udevice *dev) |
| 706 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 707 | struct eth_pdata *pdata = dev_get_plat(dev); |
Simon Glass | 3240e94 | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 708 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 709 | int ret; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 710 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 711 | ret = designware_eth_init(priv, pdata->enetaddr); |
Simon Glass | 3240e94 | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 712 | if (ret) |
| 713 | return ret; |
| 714 | ret = designware_eth_enable(priv); |
| 715 | if (ret) |
| 716 | return ret; |
| 717 | |
| 718 | return 0; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 719 | } |
| 720 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 721 | int designware_eth_send(struct udevice *dev, void *packet, int length) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 722 | { |
| 723 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 724 | |
| 725 | return _dw_eth_send(priv, packet, length); |
| 726 | } |
| 727 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 728 | int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 729 | { |
| 730 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 731 | |
| 732 | return _dw_eth_recv(priv, packetp); |
| 733 | } |
| 734 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 735 | int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 736 | { |
| 737 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 738 | |
| 739 | return _dw_free_pkt(priv); |
| 740 | } |
| 741 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 742 | void designware_eth_stop(struct udevice *dev) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 743 | { |
| 744 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 745 | |
| 746 | return _dw_eth_halt(priv); |
| 747 | } |
| 748 | |
Simon Glass | c154fc0 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 749 | int designware_eth_write_hwaddr(struct udevice *dev) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 750 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 751 | struct eth_pdata *pdata = dev_get_plat(dev); |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 752 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 753 | |
| 754 | return _dw_write_hwaddr(priv, pdata->enetaddr); |
| 755 | } |
| 756 | |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 757 | static int designware_eth_bind(struct udevice *dev) |
| 758 | { |
Simon Glass | 900f0da | 2021-08-01 18:54:34 -0600 | [diff] [blame] | 759 | if (IS_ENABLED(CONFIG_PCI)) { |
| 760 | static int num_cards; |
| 761 | char name[20]; |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 762 | |
Simon Glass | 900f0da | 2021-08-01 18:54:34 -0600 | [diff] [blame] | 763 | /* Create a unique device name for PCI type devices */ |
| 764 | if (device_is_on_pci_bus(dev)) { |
| 765 | sprintf(name, "eth_designware#%u", num_cards++); |
| 766 | device_set_name(dev, name); |
| 767 | } |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 768 | } |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 769 | |
| 770 | return 0; |
| 771 | } |
| 772 | |
Sjoerd Simons | 9cf8fd0 | 2017-01-11 11:46:07 +0100 | [diff] [blame] | 773 | int designware_eth_probe(struct udevice *dev) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 774 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 775 | struct eth_pdata *pdata = dev_get_plat(dev); |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 776 | struct dw_eth_dev *priv = dev_get_priv(dev); |
Bin Meng | dfc90f5 | 2015-09-03 05:37:29 -0700 | [diff] [blame] | 777 | u32 iobase = pdata->iobase; |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 778 | ulong ioaddr; |
Simon Goldschmidt | 313b966 | 2019-07-12 21:07:03 +0200 | [diff] [blame] | 779 | int ret, err; |
Ley Foon Tan | 27d5c00 | 2018-06-14 18:45:23 +0800 | [diff] [blame] | 780 | struct reset_ctl_bulk reset_bulk; |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 781 | #ifdef CONFIG_CLK |
Simon Goldschmidt | 313b966 | 2019-07-12 21:07:03 +0200 | [diff] [blame] | 782 | int i, clock_nb; |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 783 | |
| 784 | priv->clock_count = 0; |
Patrick Delaunay | d776a84 | 2020-09-25 09:41:14 +0200 | [diff] [blame] | 785 | clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", |
| 786 | 0); |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 787 | if (clock_nb > 0) { |
| 788 | priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), |
| 789 | GFP_KERNEL); |
| 790 | if (!priv->clocks) |
| 791 | return -ENOMEM; |
| 792 | |
| 793 | for (i = 0; i < clock_nb; i++) { |
| 794 | err = clk_get_by_index(dev, i, &priv->clocks[i]); |
| 795 | if (err < 0) |
| 796 | break; |
| 797 | |
| 798 | err = clk_enable(&priv->clocks[i]); |
Eugeniy Paltsev | 11e754e | 2018-02-06 17:12:09 +0300 | [diff] [blame] | 799 | if (err && err != -ENOSYS && err != -ENOTSUPP) { |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 800 | pr_err("failed to enable clock %d\n", i); |
| 801 | clk_free(&priv->clocks[i]); |
| 802 | goto clk_err; |
| 803 | } |
| 804 | priv->clock_count++; |
| 805 | } |
| 806 | } else if (clock_nb != -ENOENT) { |
| 807 | pr_err("failed to get clock phandle(%d)\n", clock_nb); |
| 808 | return clock_nb; |
| 809 | } |
| 810 | #endif |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 811 | |
Jacob Chen | 7ceacea | 2017-03-27 16:54:17 +0800 | [diff] [blame] | 812 | #if defined(CONFIG_DM_REGULATOR) |
| 813 | struct udevice *phy_supply; |
| 814 | |
| 815 | ret = device_get_supply_regulator(dev, "phy-supply", |
| 816 | &phy_supply); |
| 817 | if (ret) { |
| 818 | debug("%s: No phy supply\n", dev->name); |
| 819 | } else { |
| 820 | ret = regulator_set_enable(phy_supply, true); |
| 821 | if (ret) { |
| 822 | puts("Error enabling phy supply\n"); |
| 823 | return ret; |
| 824 | } |
| 825 | } |
| 826 | #endif |
| 827 | |
Ley Foon Tan | 27d5c00 | 2018-06-14 18:45:23 +0800 | [diff] [blame] | 828 | ret = reset_get_bulk(dev, &reset_bulk); |
| 829 | if (ret) |
| 830 | dev_warn(dev, "Can't get reset: %d\n", ret); |
| 831 | else |
| 832 | reset_deassert_bulk(&reset_bulk); |
| 833 | |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 834 | /* |
| 835 | * If we are on PCI bus, either directly attached to a PCI root port, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 836 | * or via a PCI bridge, fill in plat before we probe the hardware. |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 837 | */ |
Simon Glass | 900f0da | 2021-08-01 18:54:34 -0600 | [diff] [blame] | 838 | if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) { |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 839 | dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); |
| 840 | iobase &= PCI_BASE_ADDRESS_MEM_MASK; |
Bin Meng | 6c3300c | 2016-02-02 05:58:00 -0800 | [diff] [blame] | 841 | iobase = dm_pci_mem_to_phys(dev, iobase); |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 842 | |
| 843 | pdata->iobase = iobase; |
| 844 | pdata->phy_interface = PHY_INTERFACE_MODE_RMII; |
| 845 | } |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 846 | |
Bin Meng | dfc90f5 | 2015-09-03 05:37:29 -0700 | [diff] [blame] | 847 | debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); |
Beniamino Galvani | 3bfa65c | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 848 | ioaddr = iobase; |
| 849 | priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; |
| 850 | priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 851 | priv->interface = pdata->phy_interface; |
Alexey Brodkin | a3d3874 | 2016-01-13 16:59:37 +0300 | [diff] [blame] | 852 | priv->max_speed = pdata->max_speed; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 853 | |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 854 | #if IS_ENABLED(CONFIG_DM_MDIO) |
| 855 | ret = dw_dm_mdio_init(dev->name, dev); |
| 856 | #else |
Simon Goldschmidt | 313b966 | 2019-07-12 21:07:03 +0200 | [diff] [blame] | 857 | ret = dw_mdio_init(dev->name, dev); |
Neil Armstrong | 47318c9 | 2021-02-24 15:02:39 +0100 | [diff] [blame] | 858 | #endif |
Simon Goldschmidt | 313b966 | 2019-07-12 21:07:03 +0200 | [diff] [blame] | 859 | if (ret) { |
| 860 | err = ret; |
| 861 | goto mdio_err; |
| 862 | } |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 863 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 864 | |
| 865 | ret = dw_phy_init(priv, dev); |
| 866 | debug("%s, ret=%d\n", __func__, ret); |
Simon Goldschmidt | 313b966 | 2019-07-12 21:07:03 +0200 | [diff] [blame] | 867 | if (!ret) |
| 868 | return 0; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 869 | |
Simon Goldschmidt | 313b966 | 2019-07-12 21:07:03 +0200 | [diff] [blame] | 870 | /* continue here for cleanup if no PHY found */ |
| 871 | err = ret; |
| 872 | mdio_unregister(priv->bus); |
| 873 | mdio_free(priv->bus); |
| 874 | mdio_err: |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 875 | |
| 876 | #ifdef CONFIG_CLK |
| 877 | clk_err: |
| 878 | ret = clk_release_all(priv->clocks, priv->clock_count); |
| 879 | if (ret) |
| 880 | pr_err("failed to disable all clocks\n"); |
| 881 | |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 882 | #endif |
Simon Goldschmidt | 313b966 | 2019-07-12 21:07:03 +0200 | [diff] [blame] | 883 | return err; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 884 | } |
| 885 | |
Bin Meng | f0f0277 | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 886 | static int designware_eth_remove(struct udevice *dev) |
| 887 | { |
| 888 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 889 | |
| 890 | free(priv->phydev); |
| 891 | mdio_unregister(priv->bus); |
| 892 | mdio_free(priv->bus); |
| 893 | |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 894 | #ifdef CONFIG_CLK |
| 895 | return clk_release_all(priv->clocks, priv->clock_count); |
| 896 | #else |
Bin Meng | f0f0277 | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 897 | return 0; |
Patrice Chotard | eebcf8c | 2017-11-29 09:06:11 +0100 | [diff] [blame] | 898 | #endif |
Bin Meng | f0f0277 | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 899 | } |
| 900 | |
Sjoerd Simons | 9cf8fd0 | 2017-01-11 11:46:07 +0100 | [diff] [blame] | 901 | const struct eth_ops designware_eth_ops = { |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 902 | .start = designware_eth_start, |
| 903 | .send = designware_eth_send, |
| 904 | .recv = designware_eth_recv, |
| 905 | .free_pkt = designware_eth_free_pkt, |
| 906 | .stop = designware_eth_stop, |
| 907 | .write_hwaddr = designware_eth_write_hwaddr, |
| 908 | }; |
| 909 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 910 | int designware_eth_of_to_plat(struct udevice *dev) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 911 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 912 | struct dw_eth_pdata *dw_pdata = dev_get_plat(dev); |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 913 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 914 | struct dw_eth_dev *priv = dev_get_priv(dev); |
Alexey Brodkin | 57a37bc | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 915 | #endif |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 916 | struct eth_pdata *pdata = &dw_pdata->eth_pdata; |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 917 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 918 | int reset_flags = GPIOD_IS_OUT; |
Alexey Brodkin | 57a37bc | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 919 | #endif |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 920 | int ret = 0; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 921 | |
Philipp Tomsich | dcf8763 | 2017-09-11 22:04:13 +0200 | [diff] [blame] | 922 | pdata->iobase = dev_read_addr(dev); |
Marek BehĂșn | bc19477 | 2022-04-07 00:33:01 +0200 | [diff] [blame] | 923 | pdata->phy_interface = dev_read_phy_mode(dev); |
Marek BehĂșn | 48631e4 | 2022-04-07 00:33:03 +0200 | [diff] [blame] | 924 | if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 925 | return -EINVAL; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 926 | |
Philipp Tomsich | dcf8763 | 2017-09-11 22:04:13 +0200 | [diff] [blame] | 927 | pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); |
Alexey Brodkin | a3d3874 | 2016-01-13 16:59:37 +0300 | [diff] [blame] | 928 | |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 929 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Philipp Tomsich | 150005b | 2017-06-07 18:46:01 +0200 | [diff] [blame] | 930 | if (dev_read_bool(dev, "snps,reset-active-low")) |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 931 | reset_flags |= GPIOD_ACTIVE_LOW; |
| 932 | |
| 933 | ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, |
| 934 | &priv->reset_gpio, reset_flags); |
| 935 | if (ret == 0) { |
Philipp Tomsich | 150005b | 2017-06-07 18:46:01 +0200 | [diff] [blame] | 936 | ret = dev_read_u32_array(dev, "snps,reset-delays-us", |
| 937 | dw_pdata->reset_delays, 3); |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 938 | } else if (ret == -ENOENT) { |
| 939 | ret = 0; |
| 940 | } |
Alexey Brodkin | 57a37bc | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 941 | #endif |
Sjoerd Simons | 6eb4462 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 942 | |
| 943 | return ret; |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 944 | } |
| 945 | |
| 946 | static const struct udevice_id designware_eth_ids[] = { |
| 947 | { .compatible = "allwinner,sun7i-a20-gmac" }, |
Beniamino Galvani | 2fc2ef5 | 2016-08-16 11:49:50 +0200 | [diff] [blame] | 948 | { .compatible = "amlogic,meson6-dwmac" }, |
Michael Kurz | 812962b | 2017-01-22 16:04:27 +0100 | [diff] [blame] | 949 | { .compatible = "st,stm32-dwmac" }, |
Eugeniy Paltsev | 5738e94 | 2019-10-07 19:10:50 +0300 | [diff] [blame] | 950 | { .compatible = "snps,arc-dwmac-3.70a" }, |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 951 | { } |
| 952 | }; |
| 953 | |
Marek Vasut | 7e7e617 | 2015-07-25 18:42:34 +0200 | [diff] [blame] | 954 | U_BOOT_DRIVER(eth_designware) = { |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 955 | .name = "eth_designware", |
| 956 | .id = UCLASS_ETH, |
| 957 | .of_match = designware_eth_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 958 | .of_to_plat = designware_eth_of_to_plat, |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 959 | .bind = designware_eth_bind, |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 960 | .probe = designware_eth_probe, |
Bin Meng | f0f0277 | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 961 | .remove = designware_eth_remove, |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 962 | .ops = &designware_eth_ops, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 963 | .priv_auto = sizeof(struct dw_eth_dev), |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 964 | .plat_auto = sizeof(struct dw_eth_pdata), |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 965 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
| 966 | }; |
Bin Meng | ed89bd7 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 967 | |
| 968 | static struct pci_device_id supported[] = { |
| 969 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, |
| 970 | { } |
| 971 | }; |
| 972 | |
| 973 | U_BOOT_PCI_DEVICE(eth_designware, supported); |
Simon Glass | 90e627b | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 974 | #endif |