| commit | 038c9d5d26f60c7bdef37f6e7dfeee317ee62548 | [log] [tgz] |
|---|---|---|
| author | Armando Visconti <armando.visconti@st.com> | Mon Mar 26 00:09:55 2012 +0000 |
| committer | Joe Hershberger <joe.hershberger@ni.com> | Wed Apr 04 10:47:09 2012 -0500 |
| tree | 83108435981ec813e9f8bcb007237021bd8245f5 | |
| parent | ce5b7c0105dc0a0f37ad866ab93e2a3fb5fe67b1 [diff] |
net/designware: Consecutive writes must have delay This patch solves a TX/RX problem which happens at 10Mbps, due to the fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between two consecutive writes on the same register. Signed-off-by: Armando Visconti <armando.visconti@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>