blob: 8fc56c18397689dc140fe109ab5ee6bf75adce84 [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2022 Nuvoton Technology Corp.
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <asm/io.h>
9#include <asm/arch/gcr.h>
Jim Liuc32c95c2023-11-14 16:51:59 +080010#include "../common/uart.h"
Jim Liu147c0002022-09-27 16:45:15 +080011
Jim Liuc5cc4bc2023-07-04 16:00:14 +080012#define SR_MII_CTRL_SWR_BIT15 15
13
14#define DRAM_512MB_ECC_SIZE 0x1C000000ULL
15#define DRAM_512MB_SIZE 0x20000000ULL
16#define DRAM_1GB_ECC_SIZE 0x38000000ULL
17#define DRAM_1GB_SIZE 0x40000000ULL
18#define DRAM_2GB_ECC_SIZE 0x70000000ULL
19#define DRAM_2GB_SIZE 0x80000000ULL
Jim Liu25efe152023-10-23 15:02:24 +080020#define DRAM_4GB_ECC_SIZE 0xE0000000ULL
Jim Liuc5cc4bc2023-07-04 16:00:14 +080021#define DRAM_4GB_SIZE 0x100000000ULL
22
Jim Liu147c0002022-09-27 16:45:15 +080023DECLARE_GLOBAL_DATA_PTR;
24
25int board_init(void)
26{
27 return 0;
28}
29
30int dram_init(void)
31{
32 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
33
34 /*
Jim Liuc5cc4bc2023-07-04 16:00:14 +080035 * get dram active size value from bootblock.
36 * Value sent using scrpad_03 register.
37 * feature available in bootblock 0.0.6 and above.
Jim Liu147c0002022-09-27 16:45:15 +080038 */
Jim Liuc5cc4bc2023-07-04 16:00:14 +080039
40 gd->ram_size = readl(&gcr->scrpad_c);
Jim Liuc5cc4bc2023-07-04 16:00:14 +080041
Jim Liu25efe152023-10-23 15:02:24 +080042 if (gd->ram_size == 0)
Jim Liuc5cc4bc2023-07-04 16:00:14 +080043 gd->ram_size = readl(&gcr->scrpad_b);
Jim Liu25efe152023-10-23 15:02:24 +080044 else
Jim Liuc5cc4bc2023-07-04 16:00:14 +080045 gd->ram_size *= 0x100000ULL;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080046
Jim Liuc5cc4bc2023-07-04 16:00:14 +080047 debug("ram_size: %llx ", gd->ram_size);
48
Jim Liu25efe152023-10-23 15:02:24 +080049 return 0;
50}
51
52int dram_init_banksize(void)
53{
54
55 gd->bd->bi_dram[0].start = 0;
56
Jim Liuc5cc4bc2023-07-04 16:00:14 +080057 switch (gd->ram_size) {
58 case DRAM_512MB_ECC_SIZE:
59 case DRAM_512MB_SIZE:
60 case DRAM_1GB_ECC_SIZE:
61 case DRAM_1GB_SIZE:
62 case DRAM_2GB_ECC_SIZE:
63 case DRAM_2GB_SIZE:
64 gd->bd->bi_dram[0].size = gd->ram_size;
65 gd->bd->bi_dram[1].start = 0;
66 gd->bd->bi_dram[1].size = 0;
67 break;
68 case DRAM_4GB_ECC_SIZE:
Jim Liu25efe152023-10-23 15:02:24 +080069 gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080070 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
Jim Liu25efe152023-10-23 15:02:24 +080071 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
72 (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
73 /* use bank0 only */
74 gd->ram_size = DRAM_2GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080075 break;
76 case DRAM_4GB_SIZE:
77 gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
78 gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
79 gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
Jim Liu25efe152023-10-23 15:02:24 +080080 /* use bank0 only */
81 gd->ram_size = DRAM_2GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080082 break;
83 default:
84 gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
85 gd->bd->bi_dram[1].start = 0;
86 gd->bd->bi_dram[1].size = 0;
Jim Liu25efe152023-10-23 15:02:24 +080087 gd->ram_size = DRAM_1GB_SIZE;
Jim Liuc5cc4bc2023-07-04 16:00:14 +080088 break;
89 }
90
Jim Liuc5cc4bc2023-07-04 16:00:14 +080091 return 0;
92}
93
Jim Liuc32c95c2023-11-14 16:51:59 +080094int last_stage_init(void)
95{
96 board_set_console();
97
98 return 0;
99}