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git01.mediatek.com / filogic / uboot / 93326077f39d6352b382eeb5c47317d4b3e71b07 / . / arch / arm / dts / k3-am642-sk-u-boot.dtsi
blob: c277ef8abab08467b7cbf94174ca62334a4c2a39 [file] [log] [blame]
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]11 };
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]12
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]13 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-pre-ram;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]15 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]16};
17
18&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]19 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]20};
21
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]22&cbass_mcu {
23 bootph-pre-ram;
24};
25
26&main_timer0 {
27 bootph-pre-ram;
28 clock-frequency = <200000000>;
29};
30
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]31&main_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]33 chipid@14 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]35 };
36};
37
38&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]40};
41
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]42&main_i2c0_pins_default {
43 bootph-pre-ram;
44};
45
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]46&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]48};
49
50&main_uart0_pins_default {
51 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]52};
53
54&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]56};
57
58&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]60};
61
62&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]64};
65
66&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]68 k3_sysreset: sysreset-controller {
69 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]71 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]72};
73
74&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]76};
77
78&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]80};
81
82&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]84};
85
86&sdhci0 {
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]87 status = "disabled";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]89};
90
91&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]93};
94
95&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]97};
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]98
99&cpsw3g {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]101
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]102 ethernet-ports {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]104 };
105};
106
107&cpsw_port2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]109};
110
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]111&main_bcdma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]113};
114
115&main_pktdma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]117};
118
119&rgmii1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]121};
122
123&rgmii2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]125};
126
127&mdio1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]129};
130
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]131&cpsw3g_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]133};
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]134
135&main_usb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]137};
138
139&serdes_ln_ctrl {
140 u-boot,mux-autoprobe;
141};
142
143&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]144 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]145};
146
147&usb0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]148 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]149};
150
151&serdes_wiz0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]152 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]153};
154
155&serdes0_usb_link {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]156 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]157};
158
159&serdes0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]160 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]161};
162
163&serdes_refclk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]164 bootph-pre-ram;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]165};