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git01.mediatek.com / filogic / uboot / 9310ff7867016eb1182bf34ae04405c336cbe948 / . / board / ti / panda / panda_mux_data.h
blob: c05170e336026fb3b26531d4f0f5aef7cdb193c2 [file] [log] [blame]
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]1/*
2 * (C) Copyright 2010
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Balaji Krishnamoorthy <balajitk@ti.com>
6 * Aneesh V <aneesh@ti.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]26#ifndef _PANDA_MUX_DATA_H_
27#define _PANDA_MUX_DATA_H_
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]28
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]29#include <asm/arch/mux_omap4.h>
30
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame^]31
32const struct pad_conf_entry core_padconf_array_essential[] = {
33
34{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
35{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
36{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
37{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
38{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
39{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
40{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
41{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
42{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
43{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
44{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
45{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
46{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
47{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
48{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
49{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
50{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
51{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
52{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
53{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
54{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
55{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
56{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
57{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
58{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
59{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
60{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
61{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
62{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
63{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
64{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
65{UART3_TX_IRTX, (M0)} /* uart3_tx */
66
67};
68
69const struct pad_conf_entry wkup_padconf_array_essential[] = {
70
71{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
72{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
73{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
74
75};
76
77const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
78
79{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */
80
81};
82
Aneesh Vf908b632011-07-21 09:10:01 -0400[diff] [blame]83const struct pad_conf_entry core_padconf_array_non_essential[] = {
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]84 {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
85 {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */
86 {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */
87 {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */
88 {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */
89 {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */
90 {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */
91 {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */
92 {GPMC_A16, (M3)}, /* gpio_40 */
93 {GPMC_A17, (PTD | M3)}, /* gpio_41 */
94 {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */
95 {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */
96 {GPMC_A20, (IEN | M3)}, /* gpio_44 */
97 {GPMC_A21, (M3)}, /* gpio_45 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]98 {GPMC_A22, (M3)}, /* gpio_46 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]99 {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */
100 {GPMC_A24, (PTD | M3)}, /* gpio_48 */
101 {GPMC_A25, (PTD | M3)}, /* gpio_49 */
102 {GPMC_NCS0, (M3)}, /* gpio_50 */
103 {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */
104 {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */
105 {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */
106 {GPMC_NWP, (M3)}, /* gpio_54 */
107 {GPMC_CLK, (PTD | M3)}, /* gpio_55 */
108 {GPMC_NADV_ALE, (M3)}, /* gpio_56 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]109 {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */
110 {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */
111 {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]112 {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]113 {C2C_DATA11, (PTD | M3)}, /* gpio_100 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]114 {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]115 {C2C_DATA13, (PTD | M3)}, /* gpio_102 */
116 {C2C_DATA14, (M1)}, /* dsi2_te0 */
117 {C2C_DATA15, (PTD | M3)}, /* gpio_104 */
118 {HDMI_HPD, (M0)}, /* hdmi_hpd */
119 {HDMI_CEC, (M0)}, /* hdmi_cec */
120 {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */
121 {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */
122 {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
123 {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
124 {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
125 {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
126 {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
127 {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
128 {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */
129 {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */
130 {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */
131 {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */
132 {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
133 {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
134 {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
135 {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
136 {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */
137 {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */
138 {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */
Aneesh Vf908b632011-07-21 09:10:01 -0400[diff] [blame]139 {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */
140 {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */
141 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */
142 {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */
143 {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */
144 {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */
145 {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */
146 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]147 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
148 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
149 {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
150 {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
151 {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
152 {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
153 {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
154 {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]155 {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
156 {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
157 {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]158 {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */
159 {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]160 {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */
161 {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */
162 {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
163 {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
164 {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
165 {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
166 {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
167 {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
168 {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]169 {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]170 {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
171 {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */
172 {UART2_RTS, (M0)}, /* uart2_rts */
173 {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */
174 {UART2_TX, (M0)}, /* uart2_tx */
175 {HDQ_SIO, (M3)}, /* gpio_127 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]176 {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
177 {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
178 {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
179 {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
180 {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */
181 {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */
182 {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]183 {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */
184 {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
185 {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
186 {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
187 {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
188 {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
189 {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
190 {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
191 {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
192 {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
193 {UART4_RX, (IEN | M0)}, /* uart4_rx */
194 {UART4_TX, (M0)}, /* uart4_tx */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]195 {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]196 {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */
197 {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */
198 {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */
199 {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */
200 {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */
201 {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */
202 {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */
203 {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */
204 {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */
205 {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */
206 {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */
207 {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */
208 {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]209 {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]210 {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */
211 {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */
212 {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]213 {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */
214 {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]215 {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */
216 {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */
217 {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */
218 {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */
219 {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */
220 {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */
221 {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
222 {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
223 {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
224 {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]225 {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]226 {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]227 {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]228 {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */
229 {SYS_BOOT1, (M3)}, /* gpio_185 */
230 {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]231 {SYS_BOOT3, (M3)}, /* gpio_187 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]232 {SYS_BOOT4, (M3)}, /* gpio_188 */
233 {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */
234 {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
235 {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
236 {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */
237 {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */
238 {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */
239 {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */
240 {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */
241 {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */
242 {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */
243 {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */
244 {DPM_EMU10, (IEN | M5)}, /* dispc2_de */
245 {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */
246 {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */
247 {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */
248 {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */
249 {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */
250 {DPM_EMU16, (M3)}, /* gpio_27 */
251 {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
252 {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
253 {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
254};
255
Ricardo Salveti de Araujo242a92c2011-09-21 10:17:31 +0000[diff] [blame]256const struct pad_conf_entry core_padconf_array_non_essential_4430[] = {
257 {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
258};
259
260const struct pad_conf_entry core_padconf_array_non_essential_4460[] = {
261 {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */
262};
263
Aneesh Vf908b632011-07-21 09:10:01 -0400[diff] [blame]264const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]265 {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
266 {PAD1_SIM_CLK, (M0)}, /* sim_clk */
267 {PAD0_SIM_RESET, (M0)}, /* sim_reset */
268 {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */
269 {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]270 {PAD1_FREF_XTAL_IN, (M0)}, /* # */
271 {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
272 {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
273 {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
Sricharan9310ff72011-11-15 09:49:55 -0500[diff] [blame^]274 {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]275 {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]276 {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */
Steve Sakoman9bb65b52010-07-15 13:43:10 -0700[diff] [blame]277 {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
278 {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
279 {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
280 {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
281 {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
282 {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
283};
284
Ricardo Salveti de Araujo242a92c2011-09-21 10:17:31 +0000[diff] [blame]285const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
286 {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */
287};
288
Aneesh V4a03e972011-09-08 11:06:06 -0400[diff] [blame]289#endif /* _PANDA_MUX_DATA_H_ */