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git01.mediatek.com / filogic / uboot / 92bc4e04b0557f03c1d261bd9f6211764c09005a / . / arch / arm / include / asm / arch-am33xx / cpu.h
blob: 9febfa2719a94273efc8d90911ff38d302ba4535 [file] [log] [blame]
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]1/*
2 * cpu.h
3 *
4 * AM33xx specific header file
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]9 */
10
11#ifndef _AM33XX_CPU_H
12#define _AM33XX_CPU_H
13
14#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
15#include <asm/types.h>
16#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
17
18#include <asm/arch/hardware.h>
19
20#define BIT(x) (1 << x)
21#define CL_BIT(x) (0 << x)
22
23/* Timer register bits */
24#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
25#define TCLR_AR BIT(1) /* Auto reload */
26#define TCLR_PRE BIT(5) /* Pre-scaler enable */
27#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
28#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
29
30/* device type */
31#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
32#define TST_DEVICE 0x0
33#define EMU_DEVICE 0x1
34#define HS_DEVICE 0x2
35#define GP_DEVICE 0x3
36
Matt Porter691fbe32013-03-15 10:07:06 +0000[diff] [blame]37/* cpu-id for AM33XX and TI81XX family */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]38#define AM335X 0xB944
Matt Porter691fbe32013-03-15 10:07:06 +0000[diff] [blame]39#define TI81XX 0xB81E
40#define DEVICE_ID (CTRL_BASE + 0x0600)
Tom Rinif021dba2013-08-30 16:28:45 -0400[diff] [blame]41#define DEVICE_ID_MASK 0x1FFF
42
43/* MPU max frequencies */
44#define AM335X_ZCZ_300 0x1FEF
45#define AM335X_ZCZ_600 0x1FAF
46#define AM335X_ZCZ_720 0x1F2F
47#define AM335X_ZCZ_800 0x1E2F
48#define AM335X_ZCZ_1000 0x1C2F
49#define AM335X_ZCE_300 0x1FDF
50#define AM335X_ZCE_600 0x1F9F
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]51
52/* This gives the status of the boot mode pins on the evm */
53#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
54 | BIT(3) | BIT(4))
55
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]56#define PRM_RSTCTRL_RESET 0x01
Lokesh Vutlae89f1542012-05-29 19:26:41 +0000[diff] [blame]57#define PRM_RSTST_WARM_RESET_MASK 0x232
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]58
Heiko Schocher910a7222013-08-19 16:38:59 +0200[diff] [blame]59/*
60 * Watchdog:
61 * Using the prescaler, the OMAP watchdog could go for many
62 * months before firing. These limits work without scaling,
63 * with the 60 second default assumed by most tools and docs.
64 */
65#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
66#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
67#define TIMER_MARGIN_MIN 1
68
69#define PTV 0 /* prescale */
70#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
71#define WDT_WWPS_PEND_WCLR BIT(0)
72#define WDT_WWPS_PEND_WLDR BIT(2)
73#define WDT_WWPS_PEND_WTGR BIT(3)
74#define WDT_WWPS_PEND_WSPR BIT(4)
75
76#define WDT_WCLR_PRE BIT(5)
77#define WDT_WCLR_PTV_OFF 2
78
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]79#ifndef __KERNEL_STRICT_NAMES
80#ifndef __ASSEMBLY__
Ilya Yanok2ebbb862012-11-06 13:06:30 +0000[diff] [blame]81struct gpmc_cs {
82 u32 config1; /* 0x00 */
83 u32 config2; /* 0x04 */
84 u32 config3; /* 0x08 */
85 u32 config4; /* 0x0C */
86 u32 config5; /* 0x10 */
87 u32 config6; /* 0x14 */
88 u32 config7; /* 0x18 */
89 u32 nand_cmd; /* 0x1C */
90 u32 nand_adr; /* 0x20 */
91 u32 nand_dat; /* 0x24 */
92 u8 res[8]; /* blow up to 0x30 byte */
93};
94
95struct bch_res_0_3 {
96 u32 bch_result_x[4];
97};
98
99struct gpmc {
100 u8 res1[0x10];
101 u32 sysconfig; /* 0x10 */
102 u8 res2[0x4];
103 u32 irqstatus; /* 0x18 */
104 u32 irqenable; /* 0x1C */
105 u8 res3[0x20];
106 u32 timeout_control; /* 0x40 */
107 u8 res4[0xC];
108 u32 config; /* 0x50 */
109 u32 status; /* 0x54 */
110 u8 res5[0x8]; /* 0x58 */
111 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
112 u8 res6[0x14]; /* 0x1E0 */
113 u32 ecc_config; /* 0x1F4 */
114 u32 ecc_control; /* 0x1F8 */
115 u32 ecc_size_config; /* 0x1FC */
116 u32 ecc1_result; /* 0x200 */
117 u32 ecc2_result; /* 0x204 */
118 u32 ecc3_result; /* 0x208 */
119 u32 ecc4_result; /* 0x20C */
120 u32 ecc5_result; /* 0x210 */
121 u32 ecc6_result; /* 0x214 */
122 u32 ecc7_result; /* 0x218 */
123 u32 ecc8_result; /* 0x21C */
124 u32 ecc9_result; /* 0x220 */
125 u8 res7[12]; /* 0x224 */
126 u32 testmomde_ctrl; /* 0x230 */
127 u8 res8[12]; /* 0x234 */
128 struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
129};
130
131/* Used for board specific gpmc initialization */
132extern struct gpmc *gpmc_cfg;
133
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]134#ifndef CONFIG_AM43XX
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]135/* Encapsulating core pll registers */
136struct cm_wkuppll {
137 unsigned int wkclkstctrl; /* offset 0x00 */
138 unsigned int wkctrlclkctrl; /* offset 0x04 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]139 unsigned int wkgpio0clkctrl; /* offset 0x08 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]140 unsigned int wkl4wkclkctrl; /* offset 0x0c */
141 unsigned int resv2[4];
142 unsigned int idlestdpllmpu; /* offset 0x20 */
143 unsigned int resv3[2];
144 unsigned int clkseldpllmpu; /* offset 0x2c */
145 unsigned int resv4[1];
146 unsigned int idlestdpllddr; /* offset 0x34 */
147 unsigned int resv5[2];
148 unsigned int clkseldpllddr; /* offset 0x40 */
149 unsigned int resv6[4];
150 unsigned int clkseldplldisp; /* offset 0x54 */
151 unsigned int resv7[1];
152 unsigned int idlestdpllcore; /* offset 0x5c */
153 unsigned int resv8[2];
154 unsigned int clkseldpllcore; /* offset 0x68 */
155 unsigned int resv9[1];
156 unsigned int idlestdpllper; /* offset 0x70 */
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]157 unsigned int resv10[2];
158 unsigned int clkdcoldodpllper; /* offset 0x7c */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]159 unsigned int divm4dpllcore; /* offset 0x80 */
160 unsigned int divm5dpllcore; /* offset 0x84 */
161 unsigned int clkmoddpllmpu; /* offset 0x88 */
162 unsigned int clkmoddpllper; /* offset 0x8c */
163 unsigned int clkmoddpllcore; /* offset 0x90 */
164 unsigned int clkmoddpllddr; /* offset 0x94 */
165 unsigned int clkmoddplldisp; /* offset 0x98 */
166 unsigned int clkseldpllper; /* offset 0x9c */
167 unsigned int divm2dpllddr; /* offset 0xA0 */
168 unsigned int divm2dplldisp; /* offset 0xA4 */
169 unsigned int divm2dpllmpu; /* offset 0xA8 */
170 unsigned int divm2dpllper; /* offset 0xAC */
171 unsigned int resv11[1];
172 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
Patil, Rachna5f70c512012-01-22 23:47:01 +0000[diff] [blame]173 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
174 unsigned int resv12[7];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]175 unsigned int divm6dpllcore; /* offset 0xD8 */
176};
177
178/**
179 * Encapsulating peripheral functional clocks
180 * pll registers
181 */
182struct cm_perpll {
183 unsigned int l4lsclkstctrl; /* offset 0x00 */
184 unsigned int l3sclkstctrl; /* offset 0x04 */
185 unsigned int l4fwclkstctrl; /* offset 0x08 */
186 unsigned int l3clkstctrl; /* offset 0x0c */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]187 unsigned int resv1;
188 unsigned int cpgmac0clkctrl; /* offset 0x14 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]189 unsigned int lcdclkctrl; /* offset 0x18 */
190 unsigned int usb0clkctrl; /* offset 0x1C */
191 unsigned int resv2;
192 unsigned int tptc0clkctrl; /* offset 0x24 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]193 unsigned int emifclkctrl; /* offset 0x28 */
194 unsigned int ocmcramclkctrl; /* offset 0x2c */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]195 unsigned int gpmcclkctrl; /* offset 0x30 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]196 unsigned int mcasp0clkctrl; /* offset 0x34 */
197 unsigned int uart5clkctrl; /* offset 0x38 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]198 unsigned int mmc0clkctrl; /* offset 0x3C */
199 unsigned int elmclkctrl; /* offset 0x40 */
200 unsigned int i2c2clkctrl; /* offset 0x44 */
201 unsigned int i2c1clkctrl; /* offset 0x48 */
202 unsigned int spi0clkctrl; /* offset 0x4C */
203 unsigned int spi1clkctrl; /* offset 0x50 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]204 unsigned int resv3[3];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]205 unsigned int l4lsclkctrl; /* offset 0x60 */
206 unsigned int l4fwclkctrl; /* offset 0x64 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]207 unsigned int mcasp1clkctrl; /* offset 0x68 */
208 unsigned int uart1clkctrl; /* offset 0x6C */
209 unsigned int uart2clkctrl; /* offset 0x70 */
210 unsigned int uart3clkctrl; /* offset 0x74 */
211 unsigned int uart4clkctrl; /* offset 0x78 */
212 unsigned int timer7clkctrl; /* offset 0x7C */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]213 unsigned int timer2clkctrl; /* offset 0x80 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]214 unsigned int timer3clkctrl; /* offset 0x84 */
215 unsigned int timer4clkctrl; /* offset 0x88 */
216 unsigned int resv4[8];
217 unsigned int gpio1clkctrl; /* offset 0xAC */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]218 unsigned int gpio2clkctrl; /* offset 0xB0 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]219 unsigned int gpio3clkctrl; /* offset 0xB4 */
220 unsigned int resv5;
221 unsigned int tpccclkctrl; /* offset 0xBC */
222 unsigned int dcan0clkctrl; /* offset 0xC0 */
223 unsigned int dcan1clkctrl; /* offset 0xC4 */
224 unsigned int resv6[2];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]225 unsigned int emiffwclkctrl; /* offset 0xD0 */
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]226 unsigned int epwmss0clkctrl; /* offset 0xD4 */
227 unsigned int epwmss2clkctrl; /* offset 0xD8 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]228 unsigned int l3instrclkctrl; /* offset 0xDC */
229 unsigned int l3clkctrl; /* Offset 0xE0 */
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]230 unsigned int resv8[4];
231 unsigned int mmc1clkctrl; /* offset 0xF4 */
232 unsigned int mmc2clkctrl; /* offset 0xF8 */
233 unsigned int resv9[8];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]234 unsigned int l4hsclkstctrl; /* offset 0x11C */
235 unsigned int l4hsclkctrl; /* offset 0x120 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]236 unsigned int resv10[8];
Tom Rini6097fdf2012-05-21 06:46:31 +0000[diff] [blame]237 unsigned int cpswclkstctrl; /* offset 0x144 */
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]238 unsigned int lcdcclkstctrl; /* offset 0x148 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]239};
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]240
241/* Encapsulating Display pll registers */
242struct cm_dpll {
243 unsigned int resv1[2];
244 unsigned int clktimer2clk; /* offset 0x08 */
245 unsigned int resv2[10];
246 unsigned int clklcdcpixelclk; /* offset 0x34 */
247};
Lokesh Vutla83269d02013-07-30 11:36:28 +0530[diff] [blame]248#else
249/* Encapsulating core pll registers */
250struct cm_wkuppll {
251 unsigned int resv0[136];
252 unsigned int wkl4wkclkctrl; /* offset 0x220 */
253 unsigned int resv1[55];
254 unsigned int wkclkstctrl; /* offset 0x300 */
255 unsigned int resv2[15];
256 unsigned int wkup_i2c0ctrl; /* offset 0x340 */
257 unsigned int resv3;
258 unsigned int wkup_uart0ctrl; /* offset 0x348 */
259 unsigned int resv4[5];
260 unsigned int wkctrlclkctrl; /* offset 0x360 */
261 unsigned int resv5;
262 unsigned int wkgpio0clkctrl; /* offset 0x368 */
263
264 unsigned int resv6[109];
265 unsigned int clkmoddpllcore; /* offset 0x520 */
266 unsigned int idlestdpllcore; /* offset 0x524 */
267 unsigned int resv61;
268 unsigned int clkseldpllcore; /* offset 0x52C */
269 unsigned int resv7[2];
270 unsigned int divm4dpllcore; /* offset 0x538 */
271 unsigned int divm5dpllcore; /* offset 0x53C */
272 unsigned int divm6dpllcore; /* offset 0x540 */
273
274 unsigned int resv8[7];
275 unsigned int clkmoddpllmpu; /* offset 0x560 */
276 unsigned int idlestdpllmpu; /* offset 0x564 */
277 unsigned int resv9;
278 unsigned int clkseldpllmpu; /* offset 0x56c */
279 unsigned int divm2dpllmpu; /* offset 0x570 */
280
281 unsigned int resv10[11];
282 unsigned int clkmoddpllddr; /* offset 0x5A0 */
283 unsigned int idlestdpllddr; /* offset 0x5A4 */
284 unsigned int resv11;
285 unsigned int clkseldpllddr; /* offset 0x5AC */
286 unsigned int divm2dpllddr; /* offset 0x5B0 */
287
288 unsigned int resv12[11];
289 unsigned int clkmoddpllper; /* offset 0x5E0 */
290 unsigned int idlestdpllper; /* offset 0x5E4 */
291 unsigned int resv13;
292 unsigned int clkseldpllper; /* offset 0x5EC */
293 unsigned int divm2dpllper; /* offset 0x5F0 */
294 unsigned int resv14[8];
295 unsigned int clkdcoldodpllper; /* offset 0x614 */
296
297 unsigned int resv15[2];
298 unsigned int clkmoddplldisp; /* offset 0x620 */
299 unsigned int resv16[2];
300 unsigned int clkseldplldisp; /* offset 0x62C */
301 unsigned int divm2dplldisp; /* offset 0x630 */
302};
303
304/*
305 * Encapsulating peripheral functional clocks
306 * pll registers
307 */
308struct cm_perpll {
309 unsigned int l3clkstctrl; /* offset 0x00 */
310 unsigned int resv0[7];
311 unsigned int l3clkctrl; /* Offset 0x20 */
312 unsigned int resv1[7];
313 unsigned int l3instrclkctrl; /* offset 0x40 */
314 unsigned int resv2[3];
315 unsigned int ocmcramclkctrl; /* offset 0x50 */
316 unsigned int resv3[9];
317 unsigned int tpccclkctrl; /* offset 0x78 */
318 unsigned int resv4;
319 unsigned int tptc0clkctrl; /* offset 0x80 */
320
321 unsigned int resv5[7];
322 unsigned int l4hsclkctrl; /* offset 0x0A0 */
323 unsigned int resv6;
324 unsigned int l4fwclkctrl; /* offset 0x0A8 */
325 unsigned int resv7[85];
326 unsigned int l3sclkstctrl; /* offset 0x200 */
327 unsigned int resv8[7];
328 unsigned int gpmcclkctrl; /* offset 0x220 */
329 unsigned int resv9[5];
330 unsigned int mcasp0clkctrl; /* offset 0x238 */
331 unsigned int resv10;
332 unsigned int mcasp1clkctrl; /* offset 0x240 */
333 unsigned int resv11;
334 unsigned int mmc2clkctrl; /* offset 0x248 */
335 unsigned int resv12[5];
336 unsigned int usb0clkctrl; /* offset 0x260 */
337 unsigned int resv13[103];
338 unsigned int l4lsclkstctrl; /* offset 0x400 */
339 unsigned int resv14[7];
340 unsigned int l4lsclkctrl; /* offset 0x420 */
341 unsigned int resv15;
342 unsigned int dcan0clkctrl; /* offset 0x428 */
343 unsigned int resv16;
344 unsigned int dcan1clkctrl; /* offset 0x430 */
345 unsigned int resv17[13];
346 unsigned int elmclkctrl; /* offset 0x468 */
347
348 unsigned int resv18[3];
349 unsigned int gpio1clkctrl; /* offset 0x478 */
350 unsigned int resv19;
351 unsigned int gpio2clkctrl; /* offset 0x480 */
352 unsigned int resv20;
353 unsigned int gpio3clkctrl; /* offset 0x488 */
354 unsigned int resv21[7];
355
356 unsigned int i2c1clkctrl; /* offset 0x4A8 */
357 unsigned int resv22;
358 unsigned int i2c2clkctrl; /* offset 0x4B0 */
359 unsigned int resv23[3];
360 unsigned int mmc0clkctrl; /* offset 0x4C0 */
361 unsigned int resv24;
362 unsigned int mmc1clkctrl; /* offset 0x4C8 */
363
364 unsigned int resv25[13];
365 unsigned int spi0clkctrl; /* offset 0x500 */
366 unsigned int resv26;
367 unsigned int spi1clkctrl; /* offset 0x508 */
368 unsigned int resv27[9];
369 unsigned int timer2clkctrl; /* offset 0x530 */
370 unsigned int resv28;
371 unsigned int timer3clkctrl; /* offset 0x538 */
372 unsigned int resv29;
373 unsigned int timer4clkctrl; /* offset 0x540 */
374 unsigned int resv30[5];
375 unsigned int timer7clkctrl; /* offset 0x558 */
376
377 unsigned int resv31[9];
378 unsigned int uart1clkctrl; /* offset 0x580 */
379 unsigned int resv32;
380 unsigned int uart2clkctrl; /* offset 0x588 */
381 unsigned int resv33;
382 unsigned int uart3clkctrl; /* offset 0x590 */
383 unsigned int resv34;
384 unsigned int uart4clkctrl; /* offset 0x598 */
385 unsigned int resv35;
386 unsigned int uart5clkctrl; /* offset 0x5A0 */
387 unsigned int resv36[87];
388
389 unsigned int emifclkstctrl; /* offset 0x700 */
390 unsigned int resv361[7];
391 unsigned int emifclkctrl; /* offset 0x720 */
392 unsigned int resv37[3];
393 unsigned int emiffwclkctrl; /* offset 0x730 */
394 unsigned int resv371;
395 unsigned int otfaemifclkctrl; /* offset 0x738 */
396 unsigned int resv38[57];
397 unsigned int lcdclkctrl; /* offset 0x820 */
398 unsigned int resv39[183];
399 unsigned int cpswclkstctrl; /* offset 0xB00 */
400 unsigned int resv40[7];
401 unsigned int cpgmac0clkctrl; /* offset 0xB20 */
402};
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]403
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]404struct cm_device_inst {
405 unsigned int cm_clkout1_ctrl;
406 unsigned int cm_dll_ctrl;
407};
408
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]409struct cm_dpll {
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]410 unsigned int resv1;
411 unsigned int clktimer2clk; /* offset 0x04 */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]412};
Lokesh Vutla1c1a2812013-12-10 15:02:11 +0530[diff] [blame]413#endif /* CONFIG_AM43XX */
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]414
Vaibhav Hiremath2d7da5f2012-03-08 17:15:47 +0530[diff] [blame]415/* Control Module RTC registers */
416struct cm_rtc {
417 unsigned int rtcclkctrl; /* offset 0x0 */
418 unsigned int clkstctrl; /* offset 0x4 */
419};
420
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]421/* Watchdog timer registers */
422struct wd_timer {
423 unsigned int resv1[4];
424 unsigned int wdtwdsc; /* offset 0x010 */
425 unsigned int wdtwdst; /* offset 0x014 */
426 unsigned int wdtwisr; /* offset 0x018 */
427 unsigned int wdtwier; /* offset 0x01C */
428 unsigned int wdtwwer; /* offset 0x020 */
429 unsigned int wdtwclr; /* offset 0x024 */
430 unsigned int wdtwcrr; /* offset 0x028 */
431 unsigned int wdtwldr; /* offset 0x02C */
432 unsigned int wdtwtgr; /* offset 0x030 */
433 unsigned int wdtwwps; /* offset 0x034 */
434 unsigned int resv2[3];
435 unsigned int wdtwdly; /* offset 0x044 */
436 unsigned int wdtwspr; /* offset 0x048 */
437 unsigned int resv3[1];
438 unsigned int wdtwqeoi; /* offset 0x050 */
439 unsigned int wdtwqstar; /* offset 0x054 */
440 unsigned int wdtwqsta; /* offset 0x058 */
441 unsigned int wdtwqens; /* offset 0x05C */
442 unsigned int wdtwqenc; /* offset 0x060 */
443 unsigned int resv4[39];
444 unsigned int wdt_unfr; /* offset 0x100 */
445};
446
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]447/* Timer 32 bit registers */
448struct gptimer {
449 unsigned int tidr; /* offset 0x00 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]450 unsigned char res1[12];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]451 unsigned int tiocp_cfg; /* offset 0x10 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]452 unsigned char res2[12];
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]453 unsigned int tier; /* offset 0x20 */
454 unsigned int tistatr; /* offset 0x24 */
455 unsigned int tistat; /* offset 0x28 */
456 unsigned int tisr; /* offset 0x2c */
457 unsigned int tcicr; /* offset 0x30 */
458 unsigned int twer; /* offset 0x34 */
459 unsigned int tclr; /* offset 0x38 */
460 unsigned int tcrr; /* offset 0x3c */
461 unsigned int tldr; /* offset 0x40 */
462 unsigned int ttgr; /* offset 0x44 */
463 unsigned int twpc; /* offset 0x48 */
464 unsigned int tmar; /* offset 0x4c */
465 unsigned int tcar1; /* offset 0x50 */
466 unsigned int tscir; /* offset 0x54 */
467 unsigned int tcar2; /* offset 0x58 */
468};
469
470/* UART Registers */
471struct uart_sys {
472 unsigned int resv1[21];
473 unsigned int uartsyscfg; /* offset 0x54 */
474 unsigned int uartsyssts; /* offset 0x58 */
475};
476
477/* VTP Registers */
478struct vtp_reg {
479 unsigned int vtp0ctrlreg;
480};
481
482/* Control Status Register */
483struct ctrl_stat {
484 unsigned int resv1[16];
485 unsigned int statusreg; /* ofset 0x40 */
Satyanarayana, Sandhya11784752012-08-09 18:29:57 +0000[diff] [blame]486 unsigned int resv2[51];
487 unsigned int secure_emif_sdram_config; /* offset 0x0110 */
Lokesh Vutla42c213a2013-12-10 15:02:20 +0530[diff] [blame]488 unsigned int resv3[319];
489 unsigned int dev_attr;
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]490};
Steve Sakoman6229e332012-06-04 05:35:34 +0000[diff] [blame]491
492/* AM33XX GPIO registers */
493#define OMAP_GPIO_REVISION 0x0000
494#define OMAP_GPIO_SYSCONFIG 0x0010
495#define OMAP_GPIO_SYSSTATUS 0x0114
496#define OMAP_GPIO_IRQSTATUS1 0x002c
497#define OMAP_GPIO_IRQSTATUS2 0x0030
498#define OMAP_GPIO_CTRL 0x0130
499#define OMAP_GPIO_OE 0x0134
500#define OMAP_GPIO_DATAIN 0x0138
501#define OMAP_GPIO_DATAOUT 0x013c
502#define OMAP_GPIO_LEVELDETECT0 0x0140
503#define OMAP_GPIO_LEVELDETECT1 0x0144
504#define OMAP_GPIO_RISINGDETECT 0x0148
505#define OMAP_GPIO_FALLINGDETECT 0x014c
506#define OMAP_GPIO_DEBOUNCE_EN 0x0150
507#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
508#define OMAP_GPIO_CLEARDATAOUT 0x0190
509#define OMAP_GPIO_SETDATAOUT 0x0194
510
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]511/* Control Device Register */
512struct ctrl_dev {
513 unsigned int deviceid; /* offset 0x00 */
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]514 unsigned int resv1[7];
515 unsigned int usb_ctrl0; /* offset 0x20 */
516 unsigned int resv2;
517 unsigned int usb_ctrl1; /* offset 0x28 */
518 unsigned int resv3;
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]519 unsigned int macid0l; /* offset 0x30 */
520 unsigned int macid0h; /* offset 0x34 */
521 unsigned int macid1l; /* offset 0x38 */
522 unsigned int macid1h; /* offset 0x3c */
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000[diff] [blame]523 unsigned int resv4[4];
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]524 unsigned int miisel; /* offset 0x50 */
Tom Rinif021dba2013-08-30 16:28:45 -0400[diff] [blame]525 unsigned int resv5[106];
526 unsigned int efuse_sma; /* offset 0x1FC */
Chandan Nath2015c382012-07-24 12:22:17 +0000[diff] [blame]527};
Heiko Schocherc4fea292013-08-19 16:38:56 +0200[diff] [blame]528
529/* gmii_sel register defines */
530#define GMII1_SEL_MII 0x0
531#define GMII1_SEL_RMII 0x1
532#define GMII1_SEL_RGMII 0x2
533#define GMII2_SEL_MII 0x0
534#define GMII2_SEL_RMII 0x4
535#define GMII2_SEL_RGMII 0x8
536#define RGMII1_IDMODE BIT(4)
537#define RGMII2_IDMODE BIT(5)
538#define RMII1_IO_CLK_EN BIT(6)
539#define RMII2_IO_CLK_EN BIT(7)
540
541#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
542#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
543#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
544#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
545#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
546
Heiko Schocherc9a8db82013-08-19 16:38:57 +0200[diff] [blame]547/* PWMSS */
548struct pwmss_regs {
549 unsigned int idver;
550 unsigned int sysconfig;
551 unsigned int clkconfig;
552 unsigned int clkstatus;
553};
554#define ECAP_CLK_EN BIT(0)
555#define ECAP_CLK_STOP_REQ BIT(1)
556
557struct pwmss_ecap_regs {
558 unsigned int tsctr;
559 unsigned int ctrphs;
560 unsigned int cap1;
561 unsigned int cap2;
562 unsigned int cap3;
563 unsigned int cap4;
564 unsigned int resv1[4];
565 unsigned short ecctl1;
566 unsigned short ecctl2;
567};
568
569/* Capture Control register 2 */
570#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
571#define ECTRL2_MDSL_ECAP BIT(9)
572#define ECTRL2_CTRSTP_FREERUN BIT(4)
573#define ECTRL2_PLSL_LOW BIT(10)
574#define ECTRL2_SYNC_EN BIT(5)
575
Chandan Nath1c959692011-10-14 02:58:22 +0000[diff] [blame]576#endif /* __ASSEMBLY__ */
577#endif /* __KERNEL_STRICT_NAMES */
578
579#endif /* _AM33XX_CPU_H */