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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Philipp Tomsichc2448712017-03-15 12:08:44 +01002/*
3 * Copyright 2017 Theobroma Systems Design und Consulting GmbH
Philipp Tomsichc2448712017-03-15 12:08:44 +01004 */
5
6/*
7 * Execution starts on the instruction following this 4-byte header
Kever Yangb8122862017-10-10 16:21:02 +02008 * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This
9 * magic constant will be written into the final image by the rkimage
10 * tool, but we need to reserve space for it here.
Philipp Tomsichc2448712017-03-15 12:08:44 +010011 *
12 * To make life easier for everyone, we build the SPL binary with
13 * space for this 4-byte header already included in the binary.
14 */
Philipp Tomsichc2448712017-03-15 12:08:44 +010015#ifdef CONFIG_SPL_BUILD
Philipp Tomsich728aae42017-07-11 21:04:45 +020016 /*
17 * We need to add 4 bytes of space for the 'RK33' at the
18 * beginning of the executable. However, as we want to keep
19 * this generic and make it applicable to builds that are like
20 * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
Philipp Tomsich9f1a4472017-10-10 16:21:10 +020021 * TPL, but extra space needed in the SPL), we simply insert
22 * a branch-to-next-instruction-word with the expectation that
23 * the first one may be overwritten, if this is the first stage
24 * contained in the final image created with mkimage)...
Philipp Tomsich728aae42017-07-11 21:04:45 +020025 */
Philipp Tomsich9f1a4472017-10-10 16:21:10 +020026 b 1f /* if overwritten, entry-address is at the next word */
271:
28#endif
29#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
30 adr r3, entry_counter
31 ldr r0, [r3]
32 cmp r0, #1 /* check if entry_counter == 1 */
33 beq reset /* regular bootup */
34 add r0, #1
35 str r0, [r3] /* increment the entry_counter in memory */
36 mov r0, #0 /* return 0 to the BROM to signal 'OK' */
37 bx lr /* return control to the BROM */
38entry_counter:
39 .word 0
Philipp Tomsichc2448712017-03-15 12:08:44 +010040#endif
Kever Yange9277e42017-12-18 15:05:41 +080041
42#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64))
43 /* U-Boot proper of armv7 do not need this */
Philipp Tomsichc2448712017-03-15 12:08:44 +010044 b reset
Kever Yange9277e42017-12-18 15:05:41 +080045#endif
46
Kever Yangb8122862017-10-10 16:21:02 +020047#if !defined(CONFIG_ARM64)
48 /*
49 * For armv7, the addr '_start' will used as vector start address
50 * and write to VBAR register, which needs to aligned to 0x20.
51 */
Philipp Tomsich9f1a4472017-10-10 16:21:10 +020052 .align(5), 0x0
Kever Yangb8122862017-10-10 16:21:02 +020053_start:
54 ARM_VECTORS
55#endif
Kever Yange484f772017-04-20 17:03:46 +080056
Kever Yange9277e42017-12-18 15:05:41 +080057#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
Kever Yange484f772017-04-20 17:03:46 +080058 .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
59#endif