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wdenkc00b5f82002-11-03 11:12:02 +00001/*----------------------------------------------------------------------------+
Josh Boyer471573b2009-08-07 13:53:20 -04002| This source code is dual-licensed. You may use it under the terms of the
3| GNU General Public License version 2, or under the license below.
wdenkc00b5f82002-11-03 11:12:02 +00004|
wdenk544e9732004-02-06 23:19:44 +00005| This source code has been made available to you by IBM on an AS-IS
6| basis. Anyone receiving this source is licensed under IBM
7| copyrights to use it in any way he or she deems fit, including
8| copying it, modifying it, compiling it, and redistributing it either
9| with or without modifications. No license under IBM patents or
10| patent applications is to be implied by the copyright license.
wdenkc00b5f82002-11-03 11:12:02 +000011|
wdenk544e9732004-02-06 23:19:44 +000012| Any user of this software should understand that IBM cannot provide
13| technical support for this software and will not be responsible for
14| any consequences resulting from the use of this software.
wdenkc00b5f82002-11-03 11:12:02 +000015|
wdenk544e9732004-02-06 23:19:44 +000016| Any person who transfers this source code or any derivative work
17| must include the IBM copyright notice, this paragraph, and the
18| preceding two paragraphs in the transferred software.
wdenkc00b5f82002-11-03 11:12:02 +000019|
wdenk544e9732004-02-06 23:19:44 +000020| COPYRIGHT I B M CORPORATION 1999
21| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkc00b5f82002-11-03 11:12:02 +000022+----------------------------------------------------------------------------*/
23
Larry Johnson19b3d372007-12-22 15:15:13 -050024/*
25 * (C) Copyright 2006
26 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
27 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
28 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
29 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
30 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
31 *
32 * This program is free software; you can redistribute it and/or
33 * modify it under the terms of the GNU General Public License as
34 * published by the Free Software Foundation; either version 2 of
35 * the License, or (at your option) any later version.
36 *
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
41 *
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
45 * MA 02111-1307 USA
46 */
47
wdenk544e9732004-02-06 23:19:44 +000048#ifndef __PPC440_H__
wdenkc00b5f82002-11-03 11:12:02 +000049#define __PPC440_H__
50
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
Stefan Roeseeff3a0a2007-10-31 17:55:58 +010052
wdenkc00b5f82002-11-03 11:12:02 +000053/******************************************************************************
54 * DCRs & Related
55 ******************************************************************************/
56
57/*-----------------------------------------------------------------------------
wdenk544e9732004-02-06 23:19:44 +000058 | Clocking Controller
59 +----------------------------------------------------------------------------*/
wdenk544e9732004-02-06 23:19:44 +000060/* values for clkcfga register - indirect addressing of these regs */
Stefan Roese918010a2009-09-09 16:25:29 +020061#define CPR0_PLLC 0x0040
62#define CPR0_PLLD 0x0060
63#define CPR0_PRIMAD 0x0080
64#define CPR0_PRIMBD 0x00a0
65#define CPR0_OPBD 0x00c0
66#define CPR0_PERD 0x00e0
67#define CPR0_MALD 0x0100
68#define CPR0_SPCID 0x0120
69#define CPR0_ICFG 0x0140
wdenk544e9732004-02-06 23:19:44 +000070
71/* 440gx sdr register definations */
Stefan Roese918010a2009-09-09 16:25:29 +020072#define SDR0_SDSTP0 0x0020 /* */
73#define SDR0_SDSTP1 0x0021 /* */
74#define SDR0_PINSTP 0x0040
75#define SDR0_SDCS0 0x0060
Steven A. Falco606ce992008-11-20 14:37:57 -050076#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
77#define SDR0_DDRCFG 0x00e0
78#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
Stefan Roese918010a2009-09-09 16:25:29 +020079#define SDR0_EBC 0x0100
80#define SDR0_UART0 0x0120 /* UART0 Config */
81#define SDR0_UART1 0x0121 /* UART1 Config */
82#define SDR0_UART2 0x0122 /* UART2 Config */
83#define SDR0_UART3 0x0123 /* UART3 Config */
84#define SDR0_CP440 0x0180
85#define SDR0_XCR 0x01c0
86#define SDR0_XPLLC 0x01c1
87#define SDR0_XPLLD 0x01c2
88#define SDR0_SRST 0x0200
89#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
90#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
91#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
92#define SDR0_PCI0 0x01c0
93#else
94#define SDR0_PCI0 0x0300
95#endif
96#define SDR0_USB0 0x0320
97#define SDR0_CUST0 0x4000
98#define SDR0_CUST1 0x4002
99#define SDR0_PFC0 0x4100 /* Pin Function 0 */
100#define SDR0_PFC1 0x4101 /* Pin Function 1 */
101#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
wdenk544e9732004-02-06 23:19:44 +0000102
Marian Balakowicz6900eeb2006-06-30 18:35:04 +0200103#ifdef CONFIG_440GX
Stefan Roese918010a2009-09-09 16:25:29 +0200104#define SD0_AMP 0x0240
105#define SDR0_XPLLC 0x01c1
106#define SDR0_XPLLD 0x01c2
107#define SDR0_XCR 0x01c0
108#define SDR0_SDSTP2 0x4001
109#define SDR0_SDSTP3 0x4003
Marian Balakowicz6900eeb2006-06-30 18:35:04 +0200110#endif /* CONFIG_440GX */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200111
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400112/*----------------------------------------------------------------------------+
113| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
114+----------------------------------------------------------------------------*/
115#define CCR0_PRE 0x40000000
116#define CCR0_CRPE 0x08000000
117#define CCR0_DSTG 0x00200000
118#define CCR0_DAPUIB 0x00100000
119#define CCR0_DTB 0x00008000
120#define CCR0_GICBT 0x00004000
121#define CCR0_GDCBT 0x00002000
122#define CCR0_FLSTA 0x00000100
123#define CCR0_ICSLC_MASK 0x0000000C
124#define CCR0_ICSLT_MASK 0x00000003
125#define CCR1_TCS_MASK 0x00000080
126#define CCR1_TCS_INTCLK 0x00000000
127#define CCR1_TCS_EXTCLK 0x00000080
128#define MMUCR_SWOA 0x01000000
129#define MMUCR_U1TE 0x00400000
130#define MMUCR_U2SWOAE 0x00200000
131#define MMUCR_DULXE 0x00800000
132#define MMUCR_IULXE 0x00400000
133#define MMUCR_STS 0x00100000
134#define MMUCR_STID_MASK 0x000000FF
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400135
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200136#ifdef CONFIG_440SPE
Stefan Roese918010a2009-09-09 16:25:29 +0200137#undef SDR0_SDSTP2
138#define SDR0_SDSTP2 0x0022
139#undef SDR0_SDSTP3
140#define SDR0_SDSTP3 0x0023
141#define SDR0_DDR0 0x00E1
142#define SDR0_UART2 0x0122
143#define SDR0_XCR0 0x01c0
144#define SDR0_XCR1 0x01c3
145#define SDR0_XCR2 0x01c6
146#define SDR0_XPLLC0 0x01c1
147#define SDR0_XPLLD0 0x01c2
148#define SDR0_XPLLC1 0x01c4 /*notRCW - SG */
149#define SDR0_XPLLD1 0x01c5 /*notRCW - SG */
150#define SDR0_XPLLC2 0x01c7 /*notRCW - SG */
151#define SDR0_XPLLD2 0x01c8 /*notRCW - SG */
152#define SD0_AMP0 0x0240
153#define SD0_AMP1 0x0241
154#define SDR0_CUST2 0x4004
155#define SDR0_CUST3 0x4006
156#define SDR0_SDSTP4 0x4001
157#define SDR0_SDSTP5 0x4003
158#define SDR0_SDSTP6 0x4005
159#define SDR0_SDSTP7 0x4007
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200160
Stefan Roeseb39ef632007-03-08 10:06:09 +0100161#endif /* CONFIG_440SPE */
Larry Johnson19b3d372007-12-22 15:15:13 -0500162
wdenkc00b5f82002-11-03 11:12:02 +0000163/*-----------------------------------------------------------------------------
Wolfgang Denkff4b91f2005-09-25 16:01:42 +0200164 | External Bus Controller
wdenkc00b5f82002-11-03 11:12:02 +0000165 +----------------------------------------------------------------------------*/
Stefan Roese918010a2009-09-09 16:25:29 +0200166/* values for EBC0_CFGADDR register - indirect addressing of these regs */
167#define PB0CR 0x00 /* periph bank 0 config reg */
168#define PB1CR 0x01 /* periph bank 1 config reg */
169#define PB2CR 0x02 /* periph bank 2 config reg */
170#define PB3CR 0x03 /* periph bank 3 config reg */
171#define PB4CR 0x04 /* periph bank 4 config reg */
172#define PB5CR 0x05 /* periph bank 5 config reg */
173#define PB6CR 0x06 /* periph bank 6 config reg */
174#define PB7CR 0x07 /* periph bank 7 config reg */
175#define PB0AP 0x10 /* periph bank 0 access parameters */
176#define PB1AP 0x11 /* periph bank 1 access parameters */
177#define PB2AP 0x12 /* periph bank 2 access parameters */
178#define PB3AP 0x13 /* periph bank 3 access parameters */
179#define PB4AP 0x14 /* periph bank 4 access parameters */
180#define PB5AP 0x15 /* periph bank 5 access parameters */
181#define PB6AP 0x16 /* periph bank 6 access parameters */
182#define PB7AP 0x17 /* periph bank 7 access parameters */
183#define PBEAR 0x20 /* periph bus error addr reg */
184#define PBESR 0x21 /* periph bus error status reg */
Stefan Roesea8856e32007-02-20 10:57:08 +0100185#define EBC0_CFG 0x23 /* external bus configuration reg */
wdenkc00b5f82002-11-03 11:12:02 +0000186
Stefan Roese42fbddd2006-09-07 11:51:23 +0200187#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
188 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese326c9712005-08-01 16:41:48 +0200189
Stefan Roese326c9712005-08-01 16:41:48 +0200190/* PLB3 Arbiter */
Stefan Roese918010a2009-09-09 16:25:29 +0200191#define PLB3_DCR_BASE 0x070
192#define PLB3_ACR (PLB3_DCR_BASE + 0x7)
Stefan Roese326c9712005-08-01 16:41:48 +0200193
194/* PLB4 Arbiter - PowerPC440EP Pass1 */
Stefan Roese918010a2009-09-09 16:25:29 +0200195#define PLB4_DCR_BASE 0x080
196#define PLB4_ACR (PLB4_DCR_BASE + 0x1)
Stefan Roese326c9712005-08-01 16:41:48 +0200197
Stefan Roesebc7057d2007-01-05 10:40:36 +0100198#define PLB4_ACR_WRP (0x80000000 >> 7)
199
Stefan Roese363330b2005-08-04 17:09:16 +0200200/* Pin Function Control Register 1 */
201#define SDR0_PFC1 0x4101
202#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
203#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
204#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
205#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
206#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
207#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
208#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
209#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
210#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
211#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
212#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
213#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
214#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
215#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
216#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
217#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
218#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
219#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
220#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
221#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
222#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
223#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
224#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
225#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
226
227#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
228#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
229#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
230#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
231
232/* USB Control Register */
233#define SDR0_USB0 0x0320
234#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
235#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
236#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
237#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
238#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
239#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
240
Stefan Roese42fbddd2006-09-07 11:51:23 +0200241/* Miscealleneaous Function Reg. */
242#define SDR0_MFR 0x4300
243#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
244#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
245#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
246#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
247#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
248#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
249#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
250#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
251#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
252#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
253#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
254#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
255#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
256
257#define SDR0_MFR_ERRATA3_EN0 0x00800000
258#define SDR0_MFR_ERRATA3_EN1 0x00400000
259#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
260#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
261#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
262#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
263#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
264
Stefan Roese3b897fc2008-01-09 10:28:20 +0100265#define GPT0_COMP6 0x00000098
Yuri Tikhonovd3558cb2008-02-04 14:10:42 +0100266#define GPT0_COMP5 0x00000094
267#define GPT0_COMP4 0x00000090
268#define GPT0_COMP3 0x0000008C
Yuri Tikhonovfe1d91b2008-02-06 18:48:36 +0100269#define GPT0_COMP2 0x00000088
270#define GPT0_COMP1 0x00000084
Stefan Roese42fbddd2006-09-07 11:51:23 +0200271
Yuri Tikhonovd047dab2008-04-24 10:30:53 +0200272#define GPT0_MASK6 0x000000D8
273#define GPT0_MASK5 0x000000D4
274#define GPT0_MASK4 0x000000D0
275#define GPT0_MASK3 0x000000CC
276#define GPT0_MASK2 0x000000C8
277#define GPT0_MASK1 0x000000C4
278
Stefan Roese42fbddd2006-09-07 11:51:23 +0200279#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Niklaus Giger77cad902007-06-27 18:11:38 +0200280#define SDR0_USB2D0CR 0x0320
Stefan Roese42fbddd2006-09-07 11:51:23 +0200281#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
282#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
283#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
284
285#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
286#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
287#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
288
289#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
290#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
291#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
292
293/* USB2 Host Control Register */
294#define SDR0_USB2H0CR 0x0340
295#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
296#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
297#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
298#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
299
300/* Pin Function Control Register 1 */
301#define SDR0_PFC1 0x4101
302#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
303#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
304#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
305
306#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
307#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
308#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
309#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
310#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
311#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
312#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
313#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
314
315#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
316#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
317#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
318#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
319#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
320#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
321#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
322#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
323#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
324#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
325#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
326#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
327#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
328#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
329#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
330#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
331#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
332#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
333#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
334#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
335#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
336
337#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
338#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
339#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
340#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
341
342/* Ethernet PLL Configuration Register */
343#define SDR0_PFC2 0x4102
344#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
345#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
346#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
347#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
348
349#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
350#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
351#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
352#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
353#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
354#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
355#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
356#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
357
Stefan Roeseade5a512007-06-15 08:18:01 +0200358#define SDR0_PFC4 0x4104
359
Stefan Roese42fbddd2006-09-07 11:51:23 +0200360/* USB2PHY0 Control Register */
361#define SDR0_USB2PHY0CR 0x4103
362#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
363#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
364#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
365
366#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
367#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
368#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
369
370#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
371#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
372#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
373
374#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
375#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
376#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
377
378#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
379#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
380#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
381
382#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
383#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
384#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
385
386#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
387#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
388#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
389
390#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
391#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
392#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
393
394#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
395#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
396#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
397
398#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
399#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
400#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
401#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
402
403/* Miscealleneaous Function Reg. */
404#define SDR0_MFR 0x4300
405#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
406#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
407#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
408#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
409#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
410#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
411#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
412#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
413#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
414#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
415#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
416
417#define SDR0_MFR_ERRATA3_EN0 0x00800000
418#define SDR0_MFR_ERRATA3_EN1 0x00400000
419#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
420#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
421#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
422#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
423#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
424
425#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
426
Stefan Roese363330b2005-08-04 17:09:16 +0200427/* CUST1 Customer Configuration Register1 */
428#define SDR0_CUST1 0x4002
429#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
430#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
431#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
432
433/* Pin Function Control Register 0 */
434#define SDR0_PFC0 0x4100
435#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
436#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
437#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
438#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
439#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
440
441/* Pin Function Control Register 1 */
442#define SDR0_PFC1 0x4101
443#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
444#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
445#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
446#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
447#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
448#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
449#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
450#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
451#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
452#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
453#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
454#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
455#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
456#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
457#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
458#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
459#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
460#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
461#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
462#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
463#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
464#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
465#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
466#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
467
468#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
469#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
470#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
471#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
472
Stefan Roese015772c2008-03-11 15:11:43 +0100473#endif /* 440EP || 440GR || 440EPX || 440GRX */
474
Stefan Roese015772c2008-03-11 15:11:43 +0100475#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
476 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
477 defined(CONFIG_460EX) || defined(CONFIG_460GT)
478/* CUST0 Customer Configuration Register0 */
479#define SDR0_CUST0 0x4000
480#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
481#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
482#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
483#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
wdenk544e9732004-02-06 23:19:44 +0000484
Stefan Roese015772c2008-03-11 15:11:43 +0100485#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
486#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
487#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
488
489#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
490#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
491#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
492
493#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
494#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
495#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
496
497#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
498#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
499#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
500
501#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
502#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
503#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
504
505#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
506#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
507#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
508
509#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
510#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
511#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
512
513#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
514#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
515#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
516#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
517#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
518#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
519#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
520#endif
wdenk544e9732004-02-06 23:19:44 +0000521
522/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +0000523 | On-Chip Buses
524 +----------------------------------------------------------------------------*/
525/* TODO: as needed */
526
527/*-----------------------------------------------------------------------------
528 | Clocking, Power Management and Chip Control
529 +----------------------------------------------------------------------------*/
Feng Kan33384d12008-07-08 22:48:07 -0700530#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
531 defined(CONFIG_460SX)
Stefan Roese015772c2008-03-11 15:11:43 +0100532#define CNTRL_DCR_BASE 0x160
533#else
wdenkc00b5f82002-11-03 11:12:02 +0000534#define CNTRL_DCR_BASE 0x0b0
Stefan Roese015772c2008-03-11 15:11:43 +0100535#endif
Eugene O'Brien855b6d92008-04-11 10:00:35 -0400536
Stefan Roese918010a2009-09-09 16:25:29 +0200537#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
538#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000539
Stefan Roese918010a2009-09-09 16:25:29 +0200540#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
541#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
wdenkc00b5f82002-11-03 11:12:02 +0000542
Stefan Roese918010a2009-09-09 16:25:29 +0200543#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
wdenkc00b5f82002-11-03 11:12:02 +0000544
Stefan Roese918010a2009-09-09 16:25:29 +0200545#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
546#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
wdenkc00b5f82002-11-03 11:12:02 +0000547
wdenkc00b5f82002-11-03 11:12:02 +0000548/*-----------------------------------------------------------------------------
549 | DMA
550 +----------------------------------------------------------------------------*/
Stefan Roese015772c2008-03-11 15:11:43 +0100551#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
552#define DMA_DCR_BASE 0x200
553#else
wdenkc00b5f82002-11-03 11:12:02 +0000554#define DMA_DCR_BASE 0x100
Stefan Roese015772c2008-03-11 15:11:43 +0100555#endif
Stefan Roese918010a2009-09-09 16:25:29 +0200556#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
557#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
558#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
559#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
560#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
561#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
562#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
563#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */
564#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
wdenkc00b5f82002-11-03 11:12:02 +0000565
566/*-----------------------------------------------------------------------------
567 | Memory Access Layer
568 +----------------------------------------------------------------------------*/
569#define MAL_DCR_BASE 0x180
Stefan Roese918010a2009-09-09 16:25:29 +0200570#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
571#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */
572#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
573#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
574#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
575#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */
576#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
577#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
578#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
579#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
580#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */
581#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
582#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
583#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
584#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */
585#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */
586#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */
587#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */
588#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */
589#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
590#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
Stefan Roese015772c2008-03-11 15:11:43 +0100591#if defined(CONFIG_440GX) || \
592 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese918010a2009-09-09 16:25:29 +0200593#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */
594#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */
595#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */
596#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/
597#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/
598#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
599#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
600#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
601#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
602#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200603#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +0000604
605/*-----------------------------------------------------------------------------+
Stefan Roese99644742005-11-29 18:18:21 +0100606| SDR0 Bit Settings
wdenk00fe1612004-03-14 00:07:33 +0000607+-----------------------------------------------------------------------------*/
Stefan Roeseb39ef632007-03-08 10:06:09 +0100608#if defined(CONFIG_440SP)
Stefan Roeseb39ef632007-03-08 10:06:09 +0100609#define SDR0_DDR0 0x00E1
610#define SDR0_DDR0_DPLLRST 0x80000000
611#define SDR0_DDR0_DDRM_MASK 0x60000000
612#define SDR0_DDR0_DDRM_DDR1 0x20000000
613#define SDR0_DDR0_DDRM_DDR2 0x40000000
614#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
615#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
616#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
617#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
618#endif
619
Feng Kan33384d12008-07-08 22:48:07 -0700620#if defined(CONFIG_440SPE) || defined(CONFIG_460SX)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200621#define SDR0_CP440 0x0180
622#define SDR0_CP440_ERPN_MASK 0x30000000
623#define SDR0_CP440_ERPN_MASK_HI 0x3000
624#define SDR0_CP440_ERPN_MASK_LO 0x0000
625#define SDR0_CP440_ERPN_EBC 0x10000000
626#define SDR0_CP440_ERPN_EBC_HI 0x1000
627#define SDR0_CP440_ERPN_EBC_LO 0x0000
628#define SDR0_CP440_ERPN_PCI 0x20000000
629#define SDR0_CP440_ERPN_PCI_HI 0x2000
630#define SDR0_CP440_ERPN_PCI_LO 0x0000
631#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
632#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
633#define SDR0_CP440_NTO1_MASK 0x00000002
634#define SDR0_CP440_NTO1_NTOP 0x00000000
635#define SDR0_CP440_NTO1_NTO1 0x00000002
636#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
637#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200638
639#define SDR0_SDSTP0 0x0020
640#define SDR0_SDSTP0_ENG_MASK 0x80000000
641#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
642#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
643#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
644#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
645#define SDR0_SDSTP0_SRC_MASK 0x40000000
646#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
647#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
648#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
649#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
650#define SDR0_SDSTP0_SEL_MASK 0x38000000
651#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
652#define SDR0_SDSTP0_SEL_CPU 0x08000000
653#define SDR0_SDSTP0_SEL_EBC 0x28000000
654#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
655#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
656#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
657#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
658#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
659#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
660#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
661#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
662#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
663#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
664#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
665#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
666#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
667#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
668#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
669#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
670#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
671#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
672#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
673#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
674
675
676#define SDR0_SDSTP1 0x0021
677#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
678#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
679#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
680#define SDR0_SDSTP1_PERDV0_MASK 0x03000000
681#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
682#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
683#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
684#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
685#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
686#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
687#define SDR0_SDSTP1_DDR1_MODE 0x00100000
688#define SDR0_SDSTP1_DDR2_MODE 0x00200000
689#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
690#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
691#define SDR0_SDSTP1_ERPN_MASK 0x00080000
692#define SDR0_SDSTP1_ERPN_EBC 0x00000000
693#define SDR0_SDSTP1_ERPN_PCI 0x00080000
694#define SDR0_SDSTP1_PAE_MASK 0x00040000
695#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
696#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
697#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
698#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
699#define SDR0_SDSTP1_PHCE_MASK 0x00020000
700#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
701#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
702#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
703#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
704#define SDR0_SDSTP1_PISE_MASK 0x00010000
705#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
706#define SDR0_SDSTP1_PISE_ENABLE 0x00001000
707#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
708#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
709#define SDR0_SDSTP1_PCWE_MASK 0x00008000
710#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
711#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
712#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
713#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
714#define SDR0_SDSTP1_PPIM_MASK 0x00007800
715#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
716#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
717#define SDR0_SDSTP1_PR64E_MASK 0x00000400
718#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
719#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
720#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
721#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
722#define SDR0_SDSTP1_PXFS_MASK 0x00000300
723#define SDR0_SDSTP1_PXFS_100_133 0x00000000
724#define SDR0_SDSTP1_PXFS_66_100 0x00000100
725#define SDR0_SDSTP1_PXFS_50_66 0x00000200
726#define SDR0_SDSTP1_PXFS_0_50 0x00000300
727#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
728#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
729#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
730#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
731#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
732#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
733#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
734#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
735#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
736#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
737#define SDR0_SDSTP1_ETH_MASK 0x00000004
738#define SDR0_SDSTP1_ETH_10_100 0x00000000
739#define SDR0_SDSTP1_ETH_GIGA 0x00000004
740#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
741#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
742#define SDR0_SDSTP1_NTO1_MASK 0x00000001
743#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
744#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
745#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
746#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
747
748#define SDR0_SDSTP2 0x0022
749#define SDR0_SDSTP2_P1AE_MASK 0x80000000
750#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
751#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
752#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
753#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
754#define SDR0_SDSTP2_P1HCE_MASK 0x40000000
755#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
756#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
757#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
758#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
759#define SDR0_SDSTP2_P1ISE_MASK 0x20000000
760#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
761#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
762#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
763#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
764#define SDR0_SDSTP2_P1CWE_MASK 0x10000000
765#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
766#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
767#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
768#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
769#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
770#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
771#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
772#define SDR0_SDSTP2_P1R64E_MASK 0x00800000
773#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
774#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
775#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
776#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
777#define SDR0_SDSTP2_P1XFS_MASK 0x00600000
778#define SDR0_SDSTP2_P1XFS_100_133 0x00000000
779#define SDR0_SDSTP2_P1XFS_66_100 0x00200000
780#define SDR0_SDSTP2_P1XFS_50_66 0x00400000
781#define SDR0_SDSTP2_P1XFS_0_50 0x00600000
782#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
783#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
784#define SDR0_SDSTP2_P2AE_MASK 0x00040000
785#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
786#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
787#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
788#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
789#define SDR0_SDSTP2_P2HCE_MASK 0x00020000
790#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
791#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
792#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
793#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
794#define SDR0_SDSTP2_P2ISE_MASK 0x00010000
795#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
796#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
797#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
798#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
799#define SDR0_SDSTP2_P2CWE_MASK 0x00008000
800#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
801#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
802#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
803#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
804#define SDR0_SDSTP2_P2PIM_MASK 0x00007800
805#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
806#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
807#define SDR0_SDSTP2_P2XFS_MASK 0x00000300
808#define SDR0_SDSTP2_P2XFS_100_133 0x00000000
809#define SDR0_SDSTP2_P2XFS_66_100 0x00000100
810#define SDR0_SDSTP2_P2XFS_50_66 0x00000200
811#define SDR0_SDSTP2_P2XFS_0_50 0x00000100
812#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
813#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
814
815#define SDR0_SDSTP3 0x0023
816
817#define SDR0_PINSTP 0x0040
818#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
819#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
820#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
821#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
822#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
823#define SDR0_SDCS 0x0060
824#define SDR0_ECID0 0x0080
825#define SDR0_ECID1 0x0081
826#define SDR0_ECID2 0x0082
827#define SDR0_JTAG 0x00C0
828
829#define SDR0_DDR0 0x00E1
830#define SDR0_DDR0_DPLLRST 0x80000000
831#define SDR0_DDR0_DDRM_MASK 0x60000000
832#define SDR0_DDR0_DDRM_DDR1 0x20000000
833#define SDR0_DDR0_DDRM_DDR2 0x40000000
834#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
835#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
836#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
837#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
838
839#define SDR0_UART0 0x0120
840#define SDR0_UART1 0x0121
841#define SDR0_UART2 0x0122
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200842#define SDR0_SLPIPE 0x0220
843
844#define SDR0_AMP0 0x0240
845#define SDR0_AMP0_PRIORITY 0xFFFF0000
846#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
847#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
848
849#define SDR0_AMP1 0x0241
850#define SDR0_AMP1_PRIORITY 0xFC000000
851#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
852#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
853
854#define SDR0_MIRQ0 0x0260
855#define SDR0_MIRQ1 0x0261
856#define SDR0_MALTBL 0x0280
857#define SDR0_MALRBL 0x02A0
858#define SDR0_MALTBS 0x02C0
859#define SDR0_MALRBS 0x02E0
860
861/* Reserved for Customer Use */
862#define SDR0_CUST0 0x4000
863#define SDR0_CUST0_AUTONEG_MASK 0x8000000
864#define SDR0_CUST0_NO_AUTONEG 0x0000000
865#define SDR0_CUST0_AUTONEG 0x8000000
866#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
867#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
868#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
869#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
870#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
871#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
872#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
873
874#define SDR0_SDSTP4 0x4001
875#define SDR0_CUST1 0x4002
876#define SDR0_SDSTP5 0x4003
877#define SDR0_CUST2 0x4004
878#define SDR0_SDSTP6 0x4005
879#define SDR0_CUST3 0x4006
880#define SDR0_SDSTP7 0x4007
881
882#define SDR0_PFC0 0x4100
883#define SDR0_PFC0_GPIO_0 0x80000000
884#define SDR0_PFC0_PCIX0REQ2_N 0x00000000
885#define SDR0_PFC0_GPIO_1 0x40000000
886#define SDR0_PFC0_PCIX0REQ3_N 0x00000000
887#define SDR0_PFC0_GPIO_2 0x20000000
888#define SDR0_PFC0_PCIX0GNT2_N 0x00000000
889#define SDR0_PFC0_GPIO_3 0x10000000
890#define SDR0_PFC0_PCIX0GNT3_N 0x00000000
891#define SDR0_PFC0_GPIO_4 0x08000000
892#define SDR0_PFC0_PCIX1REQ2_N 0x00000000
893#define SDR0_PFC0_GPIO_5 0x04000000
894#define SDR0_PFC0_PCIX1REQ3_N 0x00000000
895#define SDR0_PFC0_GPIO_6 0x02000000
896#define SDR0_PFC0_PCIX1GNT2_N 0x00000000
897#define SDR0_PFC0_GPIO_7 0x01000000
898#define SDR0_PFC0_PCIX1GNT3_N 0x00000000
899#define SDR0_PFC0_GPIO_8 0x00800000
900#define SDR0_PFC0_PERREADY 0x00000000
901#define SDR0_PFC0_GPIO_9 0x00400000
902#define SDR0_PFC0_PERCS1_N 0x00000000
903#define SDR0_PFC0_GPIO_10 0x00200000
904#define SDR0_PFC0_PERCS2_N 0x00000000
905#define SDR0_PFC0_GPIO_11 0x00100000
906#define SDR0_PFC0_IRQ0 0x00000000
907#define SDR0_PFC0_GPIO_12 0x00080000
908#define SDR0_PFC0_IRQ1 0x00000000
909#define SDR0_PFC0_GPIO_13 0x00040000
910#define SDR0_PFC0_IRQ2 0x00000000
911#define SDR0_PFC0_GPIO_14 0x00020000
912#define SDR0_PFC0_IRQ3 0x00000000
913#define SDR0_PFC0_GPIO_15 0x00010000
914#define SDR0_PFC0_IRQ4 0x00000000
915#define SDR0_PFC0_GPIO_16 0x00008000
916#define SDR0_PFC0_IRQ5 0x00000000
917#define SDR0_PFC0_GPIO_17 0x00004000
918#define SDR0_PFC0_PERBE0_N 0x00000000
919#define SDR0_PFC0_GPIO_18 0x00002000
920#define SDR0_PFC0_PCI0GNT0_N 0x00000000
921#define SDR0_PFC0_GPIO_19 0x00001000
922#define SDR0_PFC0_PCI0GNT1_N 0x00000000
923#define SDR0_PFC0_GPIO_20 0x00000800
924#define SDR0_PFC0_PCI0REQ0_N 0x00000000
925#define SDR0_PFC0_GPIO_21 0x00000400
926#define SDR0_PFC0_PCI0REQ1_N 0x00000000
927#define SDR0_PFC0_GPIO_22 0x00000200
928#define SDR0_PFC0_PCI1GNT0_N 0x00000000
929#define SDR0_PFC0_GPIO_23 0x00000100
930#define SDR0_PFC0_PCI1GNT1_N 0x00000000
931#define SDR0_PFC0_GPIO_24 0x00000080
932#define SDR0_PFC0_PCI1REQ0_N 0x00000000
933#define SDR0_PFC0_GPIO_25 0x00000040
934#define SDR0_PFC0_PCI1REQ1_N 0x00000000
935#define SDR0_PFC0_GPIO_26 0x00000020
936#define SDR0_PFC0_PCI2GNT0_N 0x00000000
937#define SDR0_PFC0_GPIO_27 0x00000010
938#define SDR0_PFC0_PCI2GNT1_N 0x00000000
939#define SDR0_PFC0_GPIO_28 0x00000008
940#define SDR0_PFC0_PCI2REQ0_N 0x00000000
941#define SDR0_PFC0_GPIO_29 0x00000004
942#define SDR0_PFC0_PCI2REQ1_N 0x00000000
943#define SDR0_PFC0_GPIO_30 0x00000002
944#define SDR0_PFC0_UART1RX 0x00000000
945#define SDR0_PFC0_GPIO_31 0x00000001
946#define SDR0_PFC0_UART1TX 0x00000000
947
948#define SDR0_PFC1 0x4101
949#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
950#define SDR0_PFC1_UART1_DSR_DTR 0x00000000
951#define SDR0_PFC1_UART1_CTS_RTS 0x02000000
952#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
953#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
954#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
955#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
956#define SDR0_PFC1_ETH_10_100 0x00000000
957#define SDR0_PFC1_ETH_GIGA 0x00200000
958#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
959#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
960#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
961#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
962#define SDR0_PFC1_CPU_TRACE 0x00080000
963#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
964#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
965
966#define SDR0_MFR 0x4300
967#endif /* CONFIG_440SPE */
968
Stefan Roese015772c2008-03-11 15:11:43 +0100969#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
970/* Pin Function Control Register 0 (SDR0_PFC0) */
971#define SDR0_PFC0 0x4100
972#define SDR0_PFC0_DBG 0x00008000 /* debug enable */
973#define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */
974#define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */
975#define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */
976#define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */
977#define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */
978#define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */
979#define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */
980#define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */
981#define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */
982#define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */
983#define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */
984#define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */
985#define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */
986#define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */
987#define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */
988
989/* Pin Function Control Register 1 (SDR0_PFC1) */
990#define SDR0_PFC1 0x4101
991#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
992#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
993#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
994#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
995#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
996#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
997#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
998#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/
999#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/
1000#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1001#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1002#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1003
Stefan Roese048f5a62009-07-29 08:45:27 +02001004#define SDR0_ECID0 0x0080
1005#define SDR0_ECID1 0x0081
1006#define SDR0_ECID2 0x0082
1007#define SDR0_ECID3 0x0083
1008
Stefan Roese015772c2008-03-11 15:11:43 +01001009/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
1010#define SDR0_ETH_PLL 0x4102
1011#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
1012#define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */
1013#define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */
1014#define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */
1015#define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */
1016#define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16)
1017#define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */
1018#define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8)
1019#define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */
1020#define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4)
1021#define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */
1022#define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f)
1023
1024/* Ethernet Configuration Register (SDR0_ETH_CFG) */
1025#define SDR0_ETH_CFG 0x4103
1026#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
1027#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
1028#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
1029#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
1030#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
1031#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
1032#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
1033#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
1034#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
1035#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
1036#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
1037#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
1038#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
1039#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
1040#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
1041#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
1042#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
1043#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
1044#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
1045#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
1046#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
1047#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
1048#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
1049#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
1050#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
1051#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
1052#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
1053#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
1054
1055#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
1056#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
1057#define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01
1058#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
1059#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
1060
Adam Graham4900ed22008-10-08 10:12:53 -07001061/* Ethernet Status Register */
1062#define SDR0_ETH_STS 0x4104
1063
Stefan Roese015772c2008-03-11 15:11:43 +01001064/* Miscealleneaous Function Reg. (SDR0_MFR) */
1065#define SDR0_MFR 0x4300
1066#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
1067#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
1068#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
1069#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
1070#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
1071#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
1072#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
1073#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
1074#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
1075#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
1076#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
1077#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
1078#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
1079#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
1080#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
1081#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
1082#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
1083#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
1084#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
1085#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
1086
1087/* EMACx TX Status Register (SDR0_EMACxTXST)*/
1088#define SDR0_EMAC0TXST 0x4400
1089#define SDR0_EMAC1TXST 0x4401
1090#define SDR0_EMAC2TXST 0x4402
1091#define SDR0_EMAC3TXST 0x4403
1092
1093#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
1094#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
1095#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
1096#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
1097#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
1098#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
1099#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
1100#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
1101#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
1102#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
1103#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
1104#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
1105#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
1106#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
1107#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
1108#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
1109#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
1110#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
1111#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
1112#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
1113#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
1114#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
1115#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
1116#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
1117
1118/* EMACx RX Status Register (SDR0_EMACxRXST)*/
1119#define SDR0_EMAC0RXST 0x4404
1120#define SDR0_EMAC1RXST 0x4405
1121#define SDR0_EMAC2RXST 0x4406
1122#define SDR0_EMAC3RXST 0x4407
1123
1124#define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */
1125#define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */
1126#define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */
1127#define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */
1128#define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */
1129#define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23)
1130#define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */
1131#define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */
1132#define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */
1133#define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */
1134#define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/
1135#define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/
1136#define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */
1137#define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */
1138#define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */
1139#define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */
1140#define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */
1141#define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */
1142#define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */
1143#define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */
1144#define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */
1145#define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */
1146#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
1147#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
1148#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
1149#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
1150#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
1151#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
1152
1153/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
1154#define SDR0_EMAC0REJCNT 0x4408
1155#define SDR0_EMAC1REJCNT 0x4409
1156#define SDR0_EMAC2REJCNT 0x440A
1157#define SDR0_EMAC3REJCNT 0x440B
1158
1159#define SDR0_DDR0 0x00E1
1160#define SDR0_DDR0_DPLLRST 0x80000000
1161#define SDR0_DDR0_DDRM_MASK 0x60000000
1162#define SDR0_DDR0_DDRM_DDR1 0x20000000
1163#define SDR0_DDR0_DDRM_DDR2 0x40000000
1164#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1165#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1166#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1167#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
Stefan Roese8d0f6b22008-03-05 12:31:53 +01001168
1169#define AHB_TOP 0xA4
1170#define AHB_BOT 0xA5
Stefan Roese1b198df2008-06-28 14:56:17 +02001171#define SDR0_AHB_CFG 0x370
1172#define SDR0_USB2HOST_CFG 0x371
Stefan Roese015772c2008-03-11 15:11:43 +01001173#endif /* CONFIG_460EX || CONFIG_460GT */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +02001174
Stefan Roese99644742005-11-29 18:18:21 +01001175#define SDR0_SDCS_SDD (0x80000000 >> 31)
wdenk00fe1612004-03-14 00:07:33 +00001176
Stefan Roese99644742005-11-29 18:18:21 +01001177#if defined(CONFIG_440GP)
1178#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
1179#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
1180#endif /* defined(CONFIG_440GP) */
1181#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
1182#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
1183#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
1184#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
Stefan Roese42fbddd2006-09-07 11:51:23 +02001185#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1186 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese99644742005-11-29 18:18:21 +01001187#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
1188#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
1189#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
wdenk00fe1612004-03-14 00:07:33 +00001190
wdenk6148e742005-04-03 20:55:38 +00001191#define SDR0_UARTX_UXICS_MASK 0xF0000000
1192#define SDR0_UARTX_UXICS_PLB 0x20000000
1193#define SDR0_UARTX_UXEC_MASK 0x00800000
1194#define SDR0_UARTX_UXEC_INT 0x00000000
1195#define SDR0_UARTX_UXEC_EXT 0x00800000
1196#define SDR0_UARTX_UXDTE_MASK 0x00400000
1197#define SDR0_UARTX_UXDTE_DISABLE 0x00000000
1198#define SDR0_UARTX_UXDTE_ENABLE 0x00400000
1199#define SDR0_UARTX_UXDRE_MASK 0x00200000
1200#define SDR0_UARTX_UXDRE_DISABLE 0x00000000
1201#define SDR0_UARTX_UXDRE_ENABLE 0x00200000
1202#define SDR0_UARTX_UXDC_MASK 0x00100000
1203#define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
1204#define SDR0_UARTX_UXDC_CLEARED 0x00100000
1205#define SDR0_UARTX_UXDIV_MASK 0x000000FF
1206#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1207#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
wdenk00fe1612004-03-14 00:07:33 +00001208
wdenk6148e742005-04-03 20:55:38 +00001209#define SDR0_CPU440_EARV_MASK 0x30000000
1210#define SDR0_CPU440_EARV_EBC 0x10000000
1211#define SDR0_CPU440_EARV_PCI 0x20000000
1212#define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1213#define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1214#define SDR0_CPU440_NTO1_MASK 0x00000002
1215#define SDR0_CPU440_NTO1_NTOP 0x00000000
1216#define SDR0_CPU440_NTO1_NTO1 0x00000002
1217#define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1218#define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
wdenk00fe1612004-03-14 00:07:33 +00001219
wdenk6148e742005-04-03 20:55:38 +00001220#define SDR0_XCR_PAE_MASK 0x80000000
1221#define SDR0_XCR_PAE_DISABLE 0x00000000
1222#define SDR0_XCR_PAE_ENABLE 0x80000000
1223#define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1224#define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1225#define SDR0_XCR_PHCE_MASK 0x40000000
1226#define SDR0_XCR_PHCE_DISABLE 0x00000000
1227#define SDR0_XCR_PHCE_ENABLE 0x40000000
1228#define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1229#define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1230#define SDR0_XCR_PISE_MASK 0x20000000
1231#define SDR0_XCR_PISE_DISABLE 0x00000000
1232#define SDR0_XCR_PISE_ENABLE 0x20000000
1233#define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1234#define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1235#define SDR0_XCR_PCWE_MASK 0x10000000
1236#define SDR0_XCR_PCWE_DISABLE 0x00000000
1237#define SDR0_XCR_PCWE_ENABLE 0x10000000
1238#define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1239#define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1240#define SDR0_XCR_PPIM_MASK 0x0F000000
1241#define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1242#define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1243#define SDR0_XCR_PR64E_MASK 0x00800000
1244#define SDR0_XCR_PR64E_DISABLE 0x00000000
1245#define SDR0_XCR_PR64E_ENABLE 0x00800000
1246#define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1247#define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1248#define SDR0_XCR_PXFS_MASK 0x00600000
1249#define SDR0_XCR_PXFS_HIGH 0x00000000
1250#define SDR0_XCR_PXFS_MED 0x00200000
1251#define SDR0_XCR_PXFS_LOW 0x00400000
1252#define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1253#define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1254#define SDR0_XCR_PDM_MASK 0x00000040
1255#define SDR0_XCR_PDM_MULTIPOINT 0x00000000
1256#define SDR0_XCR_PDM_P2P 0x00000040
1257#define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
1258#define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
wdenk00fe1612004-03-14 00:07:33 +00001259
1260#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
wdenk6148e742005-04-03 20:55:38 +00001261#define SDR0_PFC0_GEIE_MASK 0x00003E00
1262#define SDR0_PFC0_GEIE_TRE 0x00003E00
1263#define SDR0_PFC0_GEIE_NOTRE 0x00000000
1264#define SDR0_PFC0_TRE_MASK 0x00000100
1265#define SDR0_PFC0_TRE_DISABLE 0x00000000
1266#define SDR0_PFC0_TRE_ENABLE 0x00000100
1267#define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1268#define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
wdenk00fe1612004-03-14 00:07:33 +00001269
wdenk6148e742005-04-03 20:55:38 +00001270#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
1271#define SDR0_PFC1_EPS_MASK 0x01C00000
1272#define SDR0_PFC1_EPS_GROUP0 0x00000000
1273#define SDR0_PFC1_EPS_GROUP1 0x00400000
1274#define SDR0_PFC1_EPS_GROUP2 0x00800000
1275#define SDR0_PFC1_EPS_GROUP3 0x00C00000
1276#define SDR0_PFC1_EPS_GROUP4 0x01000000
1277#define SDR0_PFC1_EPS_GROUP5 0x01400000
1278#define SDR0_PFC1_EPS_GROUP6 0x01800000
1279#define SDR0_PFC1_EPS_GROUP7 0x01C00000
1280#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1281#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1282#define SDR0_PFC1_RMII_MASK 0x00200000
1283#define SDR0_PFC1_RMII_100MBIT 0x00000000
1284#define SDR0_PFC1_RMII_10MBIT 0x00200000
1285#define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
1286#define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1287#define SDR0_PFC1_CTEMS_MASK 0x00100000
1288#define SDR0_PFC1_CTEMS_EMS 0x00000000
1289#define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
wdenk00fe1612004-03-14 00:07:33 +00001290
wdenk6148e742005-04-03 20:55:38 +00001291#define SDR0_MFR_TAH0_MASK 0x80000000
1292#define SDR0_MFR_TAH0_ENABLE 0x00000000
1293#define SDR0_MFR_TAH0_DISABLE 0x80000000
1294#define SDR0_MFR_TAH1_MASK 0x40000000
1295#define SDR0_MFR_TAH1_ENABLE 0x00000000
1296#define SDR0_MFR_TAH1_DISABLE 0x40000000
1297#define SDR0_MFR_PCM_MASK 0x20000000
1298#define SDR0_MFR_PCM_PPC440GX 0x00000000
1299#define SDR0_MFR_PCM_PPC440GP 0x20000000
1300#define SDR0_MFR_ECS_MASK 0x10000000
1301#define SDR0_MFR_ECS_INTERNAL 0x10000000
1302
Stefan Roese326c9712005-08-01 16:41:48 +02001303#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
1304#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
1305#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1306#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1307#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1308#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1309#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1310#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1311#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1312#define SDR0_MFR_ERRATA3_EN0 0x00800000
1313#define SDR0_MFR_ERRATA3_EN1 0x00400000
Stefan Roese42fbddd2006-09-07 11:51:23 +02001314#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
Stefan Roese326c9712005-08-01 16:41:48 +02001315#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
1316#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1317#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
1318#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
1319#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
Stefan Roese42fbddd2006-09-07 11:51:23 +02001320#endif
1321
1322#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1323#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1324#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1325#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
1326#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
1327#endif
1328
1329#define SDR0_MFR_ECS_MASK 0x10000000
1330#define SDR0_MFR_ECS_INTERNAL 0x10000000
1331
1332#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1333#define SDR0_SRST0 0x200
1334#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1335#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1336#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1337#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1338#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1339#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1340#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1341#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
1342#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
1343#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1344#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1345#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1346#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
1347#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
1348#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1349#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
1350#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
1351#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
1352#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
1353#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
1354#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
1355#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
1356#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
1357#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1358#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
1359#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1360#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
1361#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
1362#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
1363#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
1364#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
1365
1366#define SDR0_SRST1 0x201
1367#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
1368#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
1369#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
1370#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
1371#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
1372#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
1373#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
1374#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
1375#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
1376#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
1377#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
1378#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
1379#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
1380#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
1381#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
1382#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
1383#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
1384#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
1385#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
1386#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
1387
Stefan Roese015772c2008-03-11 15:11:43 +01001388#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1389
Stefan Roese918010a2009-09-09 16:25:29 +02001390#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */
Stefan Roese015772c2008-03-11 15:11:43 +01001391#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1392#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1393#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1394#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1395#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1396#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1397#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1398#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
1399#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
1400#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1401#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1402#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1403#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1404#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */
1405#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/
1406#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/
1407#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/
1408#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
1409#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
1410#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
1411#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
1412#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1413#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1414#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
1415#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
1416#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
1417
1418#define SDR0_SRST1 0x201
1419#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */
1420#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */
1421#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
1422#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
1423#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
1424#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
1425#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
1426#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
1427#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
1428#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
1429#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
1430#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
1431#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
1432#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
1433#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
1434#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
1435#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
1436#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
1437#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
1438#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */
1439#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */
1440#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */
1441#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */
1442#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */
1443#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */
1444#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
1445#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */
1446#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */
1447#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */
1448#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */
1449#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */
1450#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */
1451
Stefan Roese42fbddd2006-09-07 11:51:23 +02001452#else
Stefan Roese326c9712005-08-01 16:41:48 +02001453
wdenk6148e742005-04-03 20:55:38 +00001454#define SDR0_SRST_BGO 0x80000000
1455#define SDR0_SRST_PLB 0x40000000
1456#define SDR0_SRST_EBC 0x20000000
1457#define SDR0_SRST_OPB 0x10000000
1458#define SDR0_SRST_UART0 0x08000000
1459#define SDR0_SRST_UART1 0x04000000
1460#define SDR0_SRST_IIC0 0x02000000
1461#define SDR0_SRST_IIC1 0x01000000
1462#define SDR0_SRST_GPIO 0x00800000
1463#define SDR0_SRST_GPT 0x00400000
1464#define SDR0_SRST_DMC 0x00200000
1465#define SDR0_SRST_PCI 0x00100000
1466#define SDR0_SRST_EMAC0 0x00080000
1467#define SDR0_SRST_EMAC1 0x00040000
1468#define SDR0_SRST_CPM 0x00020000
1469#define SDR0_SRST_IMU 0x00010000
1470#define SDR0_SRST_UIC01 0x00008000
1471#define SDR0_SRST_UICB2 0x00004000
1472#define SDR0_SRST_SRAM 0x00002000
1473#define SDR0_SRST_EBM 0x00001000
1474#define SDR0_SRST_BGI 0x00000800
1475#define SDR0_SRST_DMA 0x00000400
1476#define SDR0_SRST_DMAC 0x00000200
1477#define SDR0_SRST_MAL 0x00000100
1478#define SDR0_SRST_ZMII 0x00000080
1479#define SDR0_SRST_GPTR 0x00000040
1480#define SDR0_SRST_PPM 0x00000020
1481#define SDR0_SRST_EMAC2 0x00000010
1482#define SDR0_SRST_EMAC3 0x00000008
1483#define SDR0_SRST_RGMII 0x00000001
wdenk00fe1612004-03-14 00:07:33 +00001484
Stefan Roese42fbddd2006-09-07 11:51:23 +02001485#endif
1486
wdenk00fe1612004-03-14 00:07:33 +00001487/*-----------------------------------------------------------------------------+
wdenkc00b5f82002-11-03 11:12:02 +00001488| Clocking
1489+-----------------------------------------------------------------------------*/
Feng Kan33384d12008-07-08 22:48:07 -07001490#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1491 defined(CONFIG_460SX)
Stefan Roese015772c2008-03-11 15:11:43 +01001492#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
1493#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
1494#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
1495#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
1496#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
1497#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1498#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
1499#elif !defined (CONFIG_440GX) && \
Stefan Roese42fbddd2006-09-07 11:51:23 +02001500 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
1501 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1502 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenk544e9732004-02-06 23:19:44 +00001503#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
1504#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
1505#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
1506#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
1507#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
1508#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
1509#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
1510#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
1511#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
1512#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
1513#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
1514#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
wdenkc00b5f82002-11-03 11:12:02 +00001515
wdenk544e9732004-02-06 23:19:44 +00001516#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1517#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1518#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1519#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
Stefan Roeseb30f2a12005-08-08 12:42:22 +02001520#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
wdenk544e9732004-02-06 23:19:44 +00001521#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
1522#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
1523#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
1524#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
1525#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
1526#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
1527#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
1528#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
1529#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
1530
Stefan Roese326c9712005-08-01 16:41:48 +02001531#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
1532#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
1533#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
1534#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
1535#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
1536#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
1537
1538#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
1539#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
1540#define PRADV_MASK 0x07000000 /* Primary Divisor A */
1541#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
1542#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
1543
wdenk544e9732004-02-06 23:19:44 +00001544#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1545#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1546#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1547#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
1548
1549/* Strap 1 Register */
1550#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
1551#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1552#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
1553#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
1554#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
1555#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
1556#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
1557#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
1558#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
1559#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
1560#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
1561#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
1562#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
1563#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
1564#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
1565#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
1566#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
1567#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
Stefan Roeseb30f2a12005-08-08 12:42:22 +02001568#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +00001569
Stefan Roese42fbddd2006-09-07 11:51:23 +02001570#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
Stefan Roeseeb1bb2e2008-06-30 14:11:07 +02001571#define CPR0_ICFG_RLI_MASK 0x80000000
1572#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
1573#define CPR0_PERD_PERDV0_MASK 0x07000000
Stefan Roese42fbddd2006-09-07 11:51:23 +02001574#endif
Stefan Roese42fbddd2006-09-07 11:51:23 +02001575
wdenkc00b5f82002-11-03 11:12:02 +00001576/*-----------------------------------------------------------------------------
1577| IIC Register Offsets
1578'----------------------------------------------------------------------------*/
wdenk6148e742005-04-03 20:55:38 +00001579#define IICMDBUF 0x00
1580#define IICSDBUF 0x02
1581#define IICLMADR 0x04
1582#define IICHMADR 0x05
1583#define IICCNTL 0x06
1584#define IICMDCNTL 0x07
1585#define IICSTS 0x08
1586#define IICEXTSTS 0x09
1587#define IICLSADR 0x0A
1588#define IICHSADR 0x0B
1589#define IICCLKDIV 0x0C
1590#define IICINTRMSK 0x0D
1591#define IICXFRCNT 0x0E
1592#define IICXTCNTLSS 0x0F
1593#define IICDIRECTCNTL 0x10
wdenkc00b5f82002-11-03 11:12:02 +00001594
1595/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +00001596| PCI Internal Registers et. al. (accessed via plb)
1597+----------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001598#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
1599#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
1600#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
1601#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
wdenkc00b5f82002-11-03 11:12:02 +00001602
Stefan Roese42fbddd2006-09-07 11:51:23 +02001603#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1604 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese326c9712005-08-01 16:41:48 +02001605
1606/* PCI Local Configuration Registers
1607 --------------------------------- */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001608#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
Stefan Roese326c9712005-08-01 16:41:48 +02001609
1610/* PCI Master Local Configuration Registers */
1611#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
1612#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
1613#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
1614#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
1615#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
1616#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
1617#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
1618#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
1619#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
1620#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
1621#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
1622#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
1623
1624/* PCI Target Local Configuration Registers */
1625#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
1626#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
1627#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
1628#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
1629
1630#else
1631
wdenk00fe1612004-03-14 00:07:33 +00001632#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
1633#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
1634#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
1635#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
1636#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
1637#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
1638#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
1639#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
1640#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
1641#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
1642#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
1643#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
1644#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
1645#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
1646#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
1647#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
1648#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
1649#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
1650#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
1651#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
1652#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
1653#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
1654#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
1655#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
1656#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
1657#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
1658#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
1659#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
wdenkc00b5f82002-11-03 11:12:02 +00001660
wdenk6148e742005-04-03 20:55:38 +00001661#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
1662#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
wdenkc00b5f82002-11-03 11:12:02 +00001663
wdenk00fe1612004-03-14 00:07:33 +00001664#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
1665#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
1666#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
wdenk6148e742005-04-03 20:55:38 +00001667#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
1668#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
wdenk00fe1612004-03-14 00:07:33 +00001669#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
1670#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
1671#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
wdenk6148e742005-04-03 20:55:38 +00001672#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
1673#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
wdenk00fe1612004-03-14 00:07:33 +00001674#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
wdenkc00b5f82002-11-03 11:12:02 +00001675
wdenk00fe1612004-03-14 00:07:33 +00001676#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
1677#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
1678#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
1679#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
1680#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
1681#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
1682#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
1683#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
1684#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
wdenkc00b5f82002-11-03 11:12:02 +00001685
wdenk00fe1612004-03-14 00:07:33 +00001686#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
wdenkc00b5f82002-11-03 11:12:02 +00001687
Stefan Roeseb30f2a12005-08-08 12:42:22 +02001688#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
Stefan Roese326c9712005-08-01 16:41:48 +02001689
Stefan Roese42fbddd2006-09-07 11:51:23 +02001690#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1691
1692/* USB2.0 Device */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001693#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE
Stefan Roese42fbddd2006-09-07 11:51:23 +02001694
1695#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
1696
1697#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
1698#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
1699#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
1700#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
1701#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
1702#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
1703#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
1704#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
1705#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
1706#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
1707#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
1708#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
1709#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
1710#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
1711#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
1712#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
1713#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
1714#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
1715#endif
1716
Stefan Roese326c9712005-08-01 16:41:48 +02001717/******************************************************************************
1718 * GPIO macro register defines
1719 ******************************************************************************/
Stefan Roesebad41112007-03-01 21:11:36 +01001720#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
Feng Kan33384d12008-07-08 22:48:07 -07001721 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1722 defined(CONFIG_460SX)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001723#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700)
Stefan Roesec443fe92005-11-22 13:20:42 +01001724
Stefan Roese9eba0c82006-06-02 16:18:04 +02001725#define GPIO0_OR (GPIO0_BASE+0x0)
1726#define GPIO0_TCR (GPIO0_BASE+0x4)
1727#define GPIO0_ODR (GPIO0_BASE+0x18)
1728#define GPIO0_IR (GPIO0_BASE+0x1C)
Stefan Roesec443fe92005-11-22 13:20:42 +01001729#endif /* CONFIG_440GP */
1730
Stefan Roese42fbddd2006-09-07 11:51:23 +02001731#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese015772c2008-03-11 15:11:43 +01001732 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1733 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001734#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
1735#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
Stefan Roese9eba0c82006-06-02 16:18:04 +02001736
Stefan Roese9eba0c82006-06-02 16:18:04 +02001737#define GPIO0_OR (GPIO0_BASE+0x0)
1738#define GPIO0_TCR (GPIO0_BASE+0x4)
1739#define GPIO0_OSRL (GPIO0_BASE+0x8)
1740#define GPIO0_OSRH (GPIO0_BASE+0xC)
1741#define GPIO0_TSRL (GPIO0_BASE+0x10)
1742#define GPIO0_TSRH (GPIO0_BASE+0x14)
1743#define GPIO0_ODR (GPIO0_BASE+0x18)
1744#define GPIO0_IR (GPIO0_BASE+0x1C)
1745#define GPIO0_RR1 (GPIO0_BASE+0x20)
1746#define GPIO0_RR2 (GPIO0_BASE+0x24)
1747#define GPIO0_RR3 (GPIO0_BASE+0x28)
1748#define GPIO0_ISR1L (GPIO0_BASE+0x30)
1749#define GPIO0_ISR1H (GPIO0_BASE+0x34)
1750#define GPIO0_ISR2L (GPIO0_BASE+0x38)
1751#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
1752#define GPIO0_ISR3L (GPIO0_BASE+0x40)
1753#define GPIO0_ISR3H (GPIO0_BASE+0x44)
1754
1755#define GPIO1_OR (GPIO1_BASE+0x0)
1756#define GPIO1_TCR (GPIO1_BASE+0x4)
1757#define GPIO1_OSRL (GPIO1_BASE+0x8)
1758#define GPIO1_OSRH (GPIO1_BASE+0xC)
1759#define GPIO1_TSRL (GPIO1_BASE+0x10)
1760#define GPIO1_TSRH (GPIO1_BASE+0x14)
1761#define GPIO1_ODR (GPIO1_BASE+0x18)
1762#define GPIO1_IR (GPIO1_BASE+0x1C)
1763#define GPIO1_RR1 (GPIO1_BASE+0x20)
1764#define GPIO1_RR2 (GPIO1_BASE+0x24)
1765#define GPIO1_RR3 (GPIO1_BASE+0x28)
1766#define GPIO1_ISR1L (GPIO1_BASE+0x30)
1767#define GPIO1_ISR1H (GPIO1_BASE+0x34)
1768#define GPIO1_ISR2L (GPIO1_BASE+0x38)
1769#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
1770#define GPIO1_ISR3L (GPIO1_BASE+0x40)
1771#define GPIO1_ISR3H (GPIO1_BASE+0x44)
Stefan Roese326c9712005-08-01 16:41:48 +02001772#endif
1773
wdenkc00b5f82002-11-03 11:12:02 +00001774#ifndef __ASSEMBLY__
1775
wdenk544e9732004-02-06 23:19:44 +00001776#endif /* _ASMLANGUAGE */
wdenkc00b5f82002-11-03 11:12:02 +00001777
wdenkc00b5f82002-11-03 11:12:02 +00001778#endif /* __PPC440_H__ */