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git01.mediatek.com / filogic / uboot / 90fecc7faa9316c7fc1d431f97352ab7203ea965 / . / arch / arm / cpu / armv7 / am33xx / clock_am33xx.c
blob: 92142c893444bc63ad7e1b811172c5996d6005a0 [file] [log] [blame]
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]1/*
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]2 * clock_am33xx.c
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]3 *
4 * clocks for AM33XX based boards
5 *
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]9 */
10
11#include <common.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/hardware.h>
15#include <asm/io.h>
16
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]17#define OSC (V_OSCK/1000000)
18
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]19struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
20struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
21struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
22struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]23
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]24const struct dpll_regs dpll_mpu_regs = {
25 .cm_clkmode_dpll = CM_WKUP + 0x88,
26 .cm_idlest_dpll = CM_WKUP + 0x20,
27 .cm_clksel_dpll = CM_WKUP + 0x2C,
28 .cm_div_m2_dpll = CM_WKUP + 0xA8,
29};
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]30
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]31const struct dpll_regs dpll_core_regs = {
32 .cm_clkmode_dpll = CM_WKUP + 0x90,
33 .cm_idlest_dpll = CM_WKUP + 0x5C,
34 .cm_clksel_dpll = CM_WKUP + 0x68,
35 .cm_div_m4_dpll = CM_WKUP + 0x80,
36 .cm_div_m5_dpll = CM_WKUP + 0x84,
37 .cm_div_m6_dpll = CM_WKUP + 0xD8,
38};
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]39
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]40const struct dpll_regs dpll_per_regs = {
41 .cm_clkmode_dpll = CM_WKUP + 0x8C,
42 .cm_idlest_dpll = CM_WKUP + 0x70,
43 .cm_clksel_dpll = CM_WKUP + 0x9C,
44 .cm_div_m2_dpll = CM_WKUP + 0xAC,
45};
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]46
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]47const struct dpll_regs dpll_ddr_regs = {
48 .cm_clkmode_dpll = CM_WKUP + 0x94,
49 .cm_idlest_dpll = CM_WKUP + 0x34,
50 .cm_clksel_dpll = CM_WKUP + 0x40,
51 .cm_div_m2_dpll = CM_WKUP + 0xA0,
52};
Matt Porter57da6662013-03-15 10:07:04 +0000[diff] [blame]53
Steve Kipisz5adac352013-08-14 10:51:31 -0400[diff] [blame]54struct dpll_params dpll_mpu_opp100 = {
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]55 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
Steve Kipisz5adac352013-08-14 10:51:31 -0400[diff] [blame]56const struct dpll_params dpll_core_opp100 = {
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]57 1000, OSC-1, -1, -1, 10, 8, 4};
Steve Kipisz5adac352013-08-14 10:51:31 -0400[diff] [blame]58const struct dpll_params dpll_mpu = {
59 MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
60const struct dpll_params dpll_core = {
61 50, OSC-1, -1, -1, 1, 1, 1};
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]62const struct dpll_params dpll_per = {
63 960, OSC-1, 5, -1, -1, -1, -1};
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]64
Lokesh Vutla42c213a2013-12-10 15:02:20 +0530[diff] [blame]65const struct dpll_params *get_dpll_mpu_params(void)
66{
67 return &dpll_mpu;
68}
69
70const struct dpll_params *get_dpll_core_params(void)
71{
72 return &dpll_core;
73}
74
75const struct dpll_params *get_dpll_per_params(void)
76{
77 return &dpll_per;
78}
79
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]80void setup_clocks_for_console(void)
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]81{
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]82 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
83 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
84 CD_CLKCTRL_CLKTRCTRL_SHIFT);
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]85
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]86 clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
87 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
88 CD_CLKCTRL_CLKTRCTRL_SHIFT);
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]89
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]90 clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
91 MODULE_CLKCTRL_MODULEMODE_MASK,
92 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
93 MODULE_CLKCTRL_MODULEMODE_SHIFT);
94 clrsetbits_le32(&cmper->uart1clkctrl,
95 MODULE_CLKCTRL_MODULEMODE_MASK,
96 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
97 MODULE_CLKCTRL_MODULEMODE_SHIFT);
98 clrsetbits_le32(&cmper->uart2clkctrl,
99 MODULE_CLKCTRL_MODULEMODE_MASK,
100 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
101 MODULE_CLKCTRL_MODULEMODE_SHIFT);
102 clrsetbits_le32(&cmper->uart3clkctrl,
103 MODULE_CLKCTRL_MODULEMODE_MASK,
104 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
105 MODULE_CLKCTRL_MODULEMODE_SHIFT);
106 clrsetbits_le32(&cmper->uart4clkctrl,
107 MODULE_CLKCTRL_MODULEMODE_MASK,
108 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
109 MODULE_CLKCTRL_MODULEMODE_SHIFT);
110 clrsetbits_le32(&cmper->uart5clkctrl,
111 MODULE_CLKCTRL_MODULEMODE_MASK,
112 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
113 MODULE_CLKCTRL_MODULEMODE_SHIFT);
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]114}
115
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]116void enable_basic_clocks(void)
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]117{
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]118 u32 *const clk_domains[] = {
119 &cmper->l3clkstctrl,
120 &cmper->l4fwclkstctrl,
121 &cmper->l3sclkstctrl,
122 &cmper->l4lsclkstctrl,
123 &cmwkup->wkclkstctrl,
124 &cmper->emiffwclkctrl,
125 &cmrtc->clkstctrl,
126 0
127 };
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]128
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]129 u32 *const clk_modules_explicit_en[] = {
130 &cmper->l3clkctrl,
131 &cmper->l4lsclkctrl,
132 &cmper->l4fwclkctrl,
133 &cmwkup->wkl4wkclkctrl,
134 &cmper->l3instrclkctrl,
135 &cmper->l4hsclkctrl,
136 &cmwkup->wkgpio0clkctrl,
137 &cmwkup->wkctrlclkctrl,
138 &cmper->timer2clkctrl,
139 &cmper->gpmcclkctrl,
140 &cmper->elmclkctrl,
141 &cmper->mmc0clkctrl,
142 &cmper->mmc1clkctrl,
143 &cmwkup->wkup_i2c0ctrl,
144 &cmper->gpio1clkctrl,
145 &cmper->gpio2clkctrl,
146 &cmper->gpio3clkctrl,
147 &cmper->i2c1clkctrl,
148 &cmper->cpgmac0clkctrl,
149 &cmper->spi0clkctrl,
150 &cmrtc->rtcclkctrl,
151 &cmper->usb0clkctrl,
152 &cmper->emiffwclkctrl,
153 &cmper->emifclkctrl,
154 0
155 };
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]156
Lokesh Vutlab1b6fba2013-07-30 10:48:53 +0530[diff] [blame]157 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]158
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]159 /* Select the Master osc 24 MHZ as Timer2 clock source */
160 writel(0x1, &cmdpll->clktimer2clk);
Chandan Nath4ba33452011-10-14 02:58:23 +0000[diff] [blame]161}