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git01.mediatek.com / filogic / uboot / 9030b3920e8a3b3b8cfcd10f33a21290718002ed / . / arch / sandbox / dts / sandbox.dts
blob: 8b50a4028983b3222008e848d7a0a45d85b5f497 [file] [log] [blame]
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]1/dts-v1/;
2
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]3#include <config.h>
4
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]5/ {
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]6 #address-cells = <1>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]7 #size-cells = <1>;
Simon Glass00c34d5b2017-06-15 21:37:53 -0600[diff] [blame]8 model = "sandbox";
Heinrich Schuchardtdeaf2972019-11-09 09:39:01 +0100[diff] [blame]9 compatible = "sandbox";
Simon Glassfd91fc92014-10-13 23:41:48 -0600[diff] [blame]10
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]11 aliases {
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]12 i2c0 = &i2c_0;
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]13 pci0 = &pcic;
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]14 rtc0 = &rtc_0;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]15 axi0 = &axi;
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]16 spi0 = &spi;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]17 };
18
Simon Glass07bb5e72019-05-18 11:59:48 -0600[diff] [blame]19 memory {
20 reg = <0 CONFIG_SYS_SDRAM_SIZE>;
21 };
22
Heinrich Schuchardtad935702020-03-14 12:13:39 +0100[diff] [blame]23 reserved-memory {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 reservation_test0 {
29 size = <0x4000>;
30 alignment = <0x2000>;
31 };
32
33 reservation_test1: restest@a000 {
34 reg = <0x00d0a000 0x2000>;
35 };
36
37 reservation_test2: restest@7000 {
38 reg = <0x00d07000 0x1000>;
39 };
40 };
41
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]42 cros_ec: cros-ec {
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]43 reg = <0 0>;
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]44 u-boot,dm-pre-reloc;
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]45 compatible = "google,cros-ec-sandbox";
Simon Glass1f6acb52014-02-27 13:25:59 -0700[diff] [blame]46 };
47
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]48 dsi_host: dsi_host {
49 compatible = "sandbox,dsi-host";
50 status = "okay";
51 };
52
Joe Hershberger89590c82018-07-02 14:47:54 -0500[diff] [blame]53 ethrawbus {
54 compatible = "sandbox,eth-raw-bus";
55 skip-localhost = <0>;
56 };
57
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]58 eth@10002000 {
59 compatible = "sandbox,eth";
60 reg = <0x10002000 0x1000>;
61 fake-host-hwaddr = [00 00 66 44 22 00];
62 };
63
Simon Glass72138b92015-04-20 12:37:28 -0600[diff] [blame]64 i2c_0: i2c@0 {
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]65 #address-cells = <1>;
66 #size-cells = <0>;
Simon Glassf905be82015-03-05 12:25:13 -0700[diff] [blame]67 reg = <0 0>;
Simon Glass4f46a592014-12-10 08:55:53 -0700[diff] [blame]68 compatible = "sandbox,i2c";
69 clock-frequency = <400000>;
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_i2c0>;
Simon Glass4d4558e2020-10-03 11:31:36 -0600[diff] [blame]72 u-boot,dm-pre-reloc;
Simon Glassfefc7ba2017-04-10 11:34:51 -0600[diff] [blame]73 };
74
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]75 pcic: pci@0 {
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]76 compatible = "sandbox,pci";
77 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]78 bus-range = <0x00 0xff>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]79 #address-cells = <3>;
80 #size-cells = <2>;
81 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
82 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Simon Glass70778bc2015-03-05 12:25:26 -0700[diff] [blame]83 };
84
Simon Glassed3698a2019-05-18 11:59:42 -0600[diff] [blame]85 spi: spi@0 {
Simon Glasse5501552018-11-06 15:21:27 -0700[diff] [blame]86 u-boot,dm-pre-reloc;
Simon Glass45ab0082015-05-22 15:42:16 -0600[diff] [blame]87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <0 0>;
90 compatible = "sandbox,spi";
91 cs-gpios = <0>, <&gpio_a 0>;
Joe Hershberger6ab76992015-03-22 17:09:13 -0500[diff] [blame]92 };
Simon Glass66c164b2014-02-26 15:59:14 -0700[diff] [blame]93};
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]94
Simon Glass28db4692019-05-18 11:59:41 -0600[diff] [blame]95#include "sandbox.dtsi"
Simon Glass73f220c2015-03-26 09:29:39 -0600[diff] [blame]96#include "cros-ec-keyboard.dtsi"
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]97#include "sandbox_pmic.dtsi"