| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2011 The Chromium OS Authors. |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __MIPS_CACHE_H__ |
| 7 | #define __MIPS_CACHE_H__ |
| 8 | |
| Daniel Schwierzeck | 02ca55e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 9 | #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT |
| 10 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
| 11 | |
| 12 | #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 13 | |
| Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 14 | /* |
| 15 | * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for |
| 16 | * DMA buffer alignment. Satisfy those drivers by providing it as a synonym |
| 17 | * of ARCH_DMA_MINALIGN for now. |
| 18 | */ |
| 19 | #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN |
| 20 | |
| Marek Vasut | fde2572 | 2016-11-25 23:32:22 +0100 | [diff] [blame] | 21 | #ifndef __ASSEMBLY__ |
| Paul Burton | dc2037e | 2016-09-21 11:18:48 +0100 | [diff] [blame] | 22 | /** |
| 23 | * mips_cache_probe() - Probe the properties of the caches |
| 24 | * |
| 25 | * Call this to probe the properties such as line sizes of the caches |
| 26 | * present in the system, if any. This must be done before cache maintenance |
| 27 | * functions such as flush_cache may be called. |
| 28 | */ |
| 29 | void mips_cache_probe(void); |
| Marek Vasut | fde2572 | 2016-11-25 23:32:22 +0100 | [diff] [blame] | 30 | #endif |
| Paul Burton | dc2037e | 2016-09-21 11:18:48 +0100 | [diff] [blame] | 31 | |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 32 | #endif /* __MIPS_CACHE_H__ */ |