| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __MIPS_CACHE_H__ |
| 8 | #define __MIPS_CACHE_H__ |
| 9 | |
| Daniel Schwierzeck | 02ca55e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 10 | #define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT |
| 11 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
| 12 | |
| 13 | #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 14 | |
| Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame^] | 15 | /* |
| 16 | * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for |
| 17 | * DMA buffer alignment. Satisfy those drivers by providing it as a synonym |
| 18 | * of ARCH_DMA_MINALIGN for now. |
| 19 | */ |
| 20 | #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN |
| 21 | |
| Anton Staaf | 66d6dbf | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 22 | #endif /* __MIPS_CACHE_H__ */ |