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Stefan Agner150ddbc2018-06-22 18:06:17 +02001/*
2 * NXP GPMI NAND flash driver (DT initialization)
3 *
4 * Copyright (C) 2018 Toradex
Ye Li30e5a502020-05-04 22:09:01 +08005 * Copyright 2019 NXP
6 *
Stefan Agner150ddbc2018-06-22 18:06:17 +02007 * Authors:
8 * Stefan Agner <stefan.agner@toradex.com>
9 *
10 * Based on denali_dt.c
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15#include <dm.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/printk.h>
Ye Li30e5a502020-05-04 22:09:01 +080019#include <clk.h>
Stefan Agner150ddbc2018-06-22 18:06:17 +020020
Shyam Sainif63ef492019-06-14 13:05:33 +053021#include <mxs_nand.h>
Stefan Agner150ddbc2018-06-22 18:06:17 +020022
23struct mxs_nand_dt_data {
24 unsigned int max_ecc_strength_supported;
Michael Trimarchifd6e13e2022-08-30 16:48:47 +020025 int max_chain_delay; /* See the async EDO mode */
Stefan Agner150ddbc2018-06-22 18:06:17 +020026};
27
Stefan Agner05413d62018-05-30 19:01:44 +020028static const struct mxs_nand_dt_data mxs_nand_imx6q_data = {
29 .max_ecc_strength_supported = 40,
Michael Trimarchifd6e13e2022-08-30 16:48:47 +020030 .max_chain_delay = 12000,
Stefan Agner05413d62018-05-30 19:01:44 +020031};
32
Ye Li960b4ba2020-05-04 22:08:56 +080033static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = {
34 .max_ecc_strength_supported = 62,
Michael Trimarchifd6e13e2022-08-30 16:48:47 +020035 .max_chain_delay = 12000,
Ye Li960b4ba2020-05-04 22:08:56 +080036};
37
Stefan Agner150ddbc2018-06-22 18:06:17 +020038static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
39 .max_ecc_strength_supported = 62,
Michael Trimarchifd6e13e2022-08-30 16:48:47 +020040 .max_chain_delay = 12000,
Stefan Agner150ddbc2018-06-22 18:06:17 +020041};
42
Peng Fan128abf42020-05-04 22:09:00 +080043static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = {
44 .max_ecc_strength_supported = 62,
Michael Trimarchifd6e13e2022-08-30 16:48:47 +020045 .max_chain_delay = 12000,
Peng Fan128abf42020-05-04 22:09:00 +080046};
47
Stefan Agner150ddbc2018-06-22 18:06:17 +020048static const struct udevice_id mxs_nand_dt_ids[] = {
49 {
Stefan Agner05413d62018-05-30 19:01:44 +020050 .compatible = "fsl,imx6q-gpmi-nand",
51 .data = (unsigned long)&mxs_nand_imx6q_data,
52 },
53 {
Han Xua231b752020-05-04 22:08:57 +080054 .compatible = "fsl,imx6qp-gpmi-nand",
55 .data = (unsigned long)&mxs_nand_imx6q_data,
56 },
57 {
Ye Li960b4ba2020-05-04 22:08:56 +080058 .compatible = "fsl,imx6sx-gpmi-nand",
59 .data = (unsigned long)&mxs_nand_imx6sx_data,
60 },
61 {
Stefan Agner150ddbc2018-06-22 18:06:17 +020062 .compatible = "fsl,imx7d-gpmi-nand",
63 .data = (unsigned long)&mxs_nand_imx7d_data,
64 },
Peng Fan128abf42020-05-04 22:09:00 +080065 {
66 .compatible = "fsl,imx8qxp-gpmi-nand",
67 .data = (unsigned long)&mxs_nand_imx8qxp_data,
68 },
Stefan Agner150ddbc2018-06-22 18:06:17 +020069 { /* sentinel */ }
70};
71
72static int mxs_nand_dt_probe(struct udevice *dev)
73{
74 struct mxs_nand_info *info = dev_get_priv(dev);
75 const struct mxs_nand_dt_data *data;
76 struct resource res;
77 int ret;
78
79 data = (void *)dev_get_driver_data(dev);
Michael Trimarchifd6e13e2022-08-30 16:48:47 +020080 if (data) {
Stefan Agner150ddbc2018-06-22 18:06:17 +020081 info->max_ecc_strength_supported = data->max_ecc_strength_supported;
Michael Trimarchifd6e13e2022-08-30 16:48:47 +020082 info->max_chain_delay = data->max_chain_delay;
83 }
Stefan Agner150ddbc2018-06-22 18:06:17 +020084
85 info->dev = dev;
86
87 ret = dev_read_resource_byname(dev, "gpmi-nand", &res);
88 if (ret)
89 return ret;
90
91 info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));
92
Stefan Agner150ddbc2018-06-22 18:06:17 +020093 ret = dev_read_resource_byname(dev, "bch", &res);
94 if (ret)
95 return ret;
96
97 info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res));
98
99 info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
100
Michael Trimarchifd6e13e2022-08-30 16:48:47 +0200101 if (IS_ENABLED(CONFIG_CLK) &&
102 (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) {
Ye Li30e5a502020-05-04 22:09:01 +0800103 /* Assigned clock already set clock */
104 struct clk gpmi_clk;
105
Michael Trimarchifd6e13e2022-08-30 16:48:47 +0200106 info->gpmi_clk = devm_clk_get(dev, "gpmi_io");
107
108 if (IS_ERR(info->gpmi_clk)) {
109 ret = PTR_ERR(info->gpmi_clk);
Ye Li30e5a502020-05-04 22:09:01 +0800110 debug("Can't get gpmi io clk: %d\n", ret);
111 return ret;
112 }
113
Michael Trimarchifd6e13e2022-08-30 16:48:47 +0200114 ret = clk_enable(info->gpmi_clk);
Ye Li30e5a502020-05-04 22:09:01 +0800115 if (ret < 0) {
116 debug("Can't enable gpmi io clk: %d\n", ret);
117 return ret;
118 }
119
Michael Trimarchifd6e13e2022-08-30 16:48:47 +0200120 if (IS_ENABLED(CONFIG_IMX8)) {
121 ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk);
122 if (ret < 0) {
123 debug("Can't get gpmi_apb clk: %d\n", ret);
124 return ret;
125 }
Ye Li30e5a502020-05-04 22:09:01 +0800126
Michael Trimarchifd6e13e2022-08-30 16:48:47 +0200127 ret = clk_enable(&gpmi_clk);
128 if (ret < 0) {
129 debug("Can't enable gpmi_apb clk: %d\n", ret);
130 return ret;
131 }
Ye Li30e5a502020-05-04 22:09:01 +0800132
Michael Trimarchifd6e13e2022-08-30 16:48:47 +0200133 ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk);
134 if (ret < 0) {
135 debug("Can't get gpmi_bch clk: %d\n", ret);
136 return ret;
137 }
Ye Li30e5a502020-05-04 22:09:01 +0800138
Michael Trimarchifd6e13e2022-08-30 16:48:47 +0200139 ret = clk_enable(&gpmi_clk);
140 if (ret < 0) {
141 debug("Can't enable gpmi_bch clk: %d\n", ret);
142 return ret;
143 }
Ye Li30e5a502020-05-04 22:09:01 +0800144 }
145
Dario Binacchi8a6bbc52022-09-27 11:56:33 +0200146 ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk);
Ye Li30e5a502020-05-04 22:09:01 +0800147 if (ret < 0) {
Dario Binacchi8a6bbc52022-09-27 11:56:33 +0200148 debug("Can't get gpmi_bch_apb clk: %d\n", ret);
Ye Li30e5a502020-05-04 22:09:01 +0800149 return ret;
150 }
151
152 ret = clk_enable(&gpmi_clk);
153 if (ret < 0) {
Dario Binacchi8a6bbc52022-09-27 11:56:33 +0200154 debug("Can't enable gpmi_bch_apb clk: %d\n", ret);
Ye Li30e5a502020-05-04 22:09:01 +0800155 return ret;
156 }
Ye Li30e5a502020-05-04 22:09:01 +0800157 }
158
Stefan Agner150ddbc2018-06-22 18:06:17 +0200159 return mxs_nand_init_ctrl(info);
160}
161
162U_BOOT_DRIVER(mxs_nand_dt) = {
163 .name = "mxs-nand-dt",
164 .id = UCLASS_MTD,
165 .of_match = mxs_nand_dt_ids,
166 .probe = mxs_nand_dt_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700167 .priv_auto = sizeof(struct mxs_nand_info),
Stefan Agner150ddbc2018-06-22 18:06:17 +0200168};
169
170void board_nand_init(void)
171{
172 struct udevice *dev;
173 int ret;
174
175 ret = uclass_get_device_by_driver(UCLASS_MTD,
Simon Glass65130cd2020-12-28 20:34:56 -0700176 DM_DRIVER_GET(mxs_nand_dt),
Stefan Agner150ddbc2018-06-22 18:06:17 +0200177 &dev);
178 if (ret && ret != -ENODEV)
179 pr_err("Failed to initialize MXS NAND controller. (error %d)\n",
180 ret);
181}