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Stefan Agner150ddbc2018-06-22 18:06:17 +02001/*
2 * NXP GPMI NAND flash driver (DT initialization)
3 *
4 * Copyright (C) 2018 Toradex
Ye Li30e5a502020-05-04 22:09:01 +08005 * Copyright 2019 NXP
6 *
Stefan Agner150ddbc2018-06-22 18:06:17 +02007 * Authors:
8 * Stefan Agner <stefan.agner@toradex.com>
9 *
10 * Based on denali_dt.c
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15#include <dm.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/printk.h>
Ye Li30e5a502020-05-04 22:09:01 +080019#include <clk.h>
Stefan Agner150ddbc2018-06-22 18:06:17 +020020
Shyam Sainif63ef492019-06-14 13:05:33 +053021#include <mxs_nand.h>
Stefan Agner150ddbc2018-06-22 18:06:17 +020022
23struct mxs_nand_dt_data {
24 unsigned int max_ecc_strength_supported;
25};
26
Stefan Agner05413d62018-05-30 19:01:44 +020027static const struct mxs_nand_dt_data mxs_nand_imx6q_data = {
28 .max_ecc_strength_supported = 40,
29};
30
Ye Li960b4ba2020-05-04 22:08:56 +080031static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = {
32 .max_ecc_strength_supported = 62,
33};
34
Stefan Agner150ddbc2018-06-22 18:06:17 +020035static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
36 .max_ecc_strength_supported = 62,
37};
38
Peng Fan128abf42020-05-04 22:09:00 +080039static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = {
40 .max_ecc_strength_supported = 62,
41};
42
Stefan Agner150ddbc2018-06-22 18:06:17 +020043static const struct udevice_id mxs_nand_dt_ids[] = {
44 {
Stefan Agner05413d62018-05-30 19:01:44 +020045 .compatible = "fsl,imx6q-gpmi-nand",
46 .data = (unsigned long)&mxs_nand_imx6q_data,
47 },
48 {
Han Xua231b752020-05-04 22:08:57 +080049 .compatible = "fsl,imx6qp-gpmi-nand",
50 .data = (unsigned long)&mxs_nand_imx6q_data,
51 },
52 {
Ye Li960b4ba2020-05-04 22:08:56 +080053 .compatible = "fsl,imx6sx-gpmi-nand",
54 .data = (unsigned long)&mxs_nand_imx6sx_data,
55 },
56 {
Stefan Agner150ddbc2018-06-22 18:06:17 +020057 .compatible = "fsl,imx7d-gpmi-nand",
58 .data = (unsigned long)&mxs_nand_imx7d_data,
59 },
Peng Fan128abf42020-05-04 22:09:00 +080060 {
61 .compatible = "fsl,imx8qxp-gpmi-nand",
62 .data = (unsigned long)&mxs_nand_imx8qxp_data,
63 },
Stefan Agner150ddbc2018-06-22 18:06:17 +020064 { /* sentinel */ }
65};
66
67static int mxs_nand_dt_probe(struct udevice *dev)
68{
69 struct mxs_nand_info *info = dev_get_priv(dev);
70 const struct mxs_nand_dt_data *data;
71 struct resource res;
72 int ret;
73
74 data = (void *)dev_get_driver_data(dev);
75 if (data)
76 info->max_ecc_strength_supported = data->max_ecc_strength_supported;
77
78 info->dev = dev;
79
80 ret = dev_read_resource_byname(dev, "gpmi-nand", &res);
81 if (ret)
82 return ret;
83
84 info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));
85
86
87 ret = dev_read_resource_byname(dev, "bch", &res);
88 if (ret)
89 return ret;
90
91 info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res));
92
93 info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
94
Ye Li30e5a502020-05-04 22:09:01 +080095 if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) {
96 /* Assigned clock already set clock */
97 struct clk gpmi_clk;
98
99 ret = clk_get_by_name(dev, "gpmi_io", &gpmi_clk);
100 if (ret < 0) {
101 debug("Can't get gpmi io clk: %d\n", ret);
102 return ret;
103 }
104
105 ret = clk_enable(&gpmi_clk);
106 if (ret < 0) {
107 debug("Can't enable gpmi io clk: %d\n", ret);
108 return ret;
109 }
110
111 ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk);
112 if (ret < 0) {
113 debug("Can't get gpmi_apb clk: %d\n", ret);
114 return ret;
115 }
116
117 ret = clk_enable(&gpmi_clk);
118 if (ret < 0) {
119 debug("Can't enable gpmi_apb clk: %d\n", ret);
120 return ret;
121 }
122
123 ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk);
124 if (ret < 0) {
125 debug("Can't get gpmi_bch clk: %d\n", ret);
126 return ret;
127 }
128
129 ret = clk_enable(&gpmi_clk);
130 if (ret < 0) {
131 debug("Can't enable gpmi_bch clk: %d\n", ret);
132 return ret;
133 }
134
Dario Binacchi8a6bbc52022-09-27 11:56:33 +0200135 ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk);
Ye Li30e5a502020-05-04 22:09:01 +0800136 if (ret < 0) {
Dario Binacchi8a6bbc52022-09-27 11:56:33 +0200137 debug("Can't get gpmi_bch_apb clk: %d\n", ret);
Ye Li30e5a502020-05-04 22:09:01 +0800138 return ret;
139 }
140
141 ret = clk_enable(&gpmi_clk);
142 if (ret < 0) {
Dario Binacchi8a6bbc52022-09-27 11:56:33 +0200143 debug("Can't enable gpmi_bch_apb clk: %d\n", ret);
Ye Li30e5a502020-05-04 22:09:01 +0800144 return ret;
145 }
Ye Li30e5a502020-05-04 22:09:01 +0800146 }
147
Stefan Agner150ddbc2018-06-22 18:06:17 +0200148 return mxs_nand_init_ctrl(info);
149}
150
151U_BOOT_DRIVER(mxs_nand_dt) = {
152 .name = "mxs-nand-dt",
153 .id = UCLASS_MTD,
154 .of_match = mxs_nand_dt_ids,
155 .probe = mxs_nand_dt_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700156 .priv_auto = sizeof(struct mxs_nand_info),
Stefan Agner150ddbc2018-06-22 18:06:17 +0200157};
158
159void board_nand_init(void)
160{
161 struct udevice *dev;
162 int ret;
163
164 ret = uclass_get_device_by_driver(UCLASS_MTD,
Simon Glass65130cd2020-12-28 20:34:56 -0700165 DM_DRIVER_GET(mxs_nand_dt),
Stefan Agner150ddbc2018-06-22 18:06:17 +0200166 &dev);
167 if (ret && ret != -ENODEV)
168 pr_err("Failed to initialize MXS NAND controller. (error %d)\n",
169 ret);
170}