Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Board functions for TI AM335X based pxm2 board |
| 4 | * (C) Copyright 2013 Siemens Schweiz AG |
| 5 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 6 | * |
| 7 | * Based on: |
| 8 | * u-boot:/board/ti/am335x/board.c |
| 9 | * |
| 10 | * Board functions for TI AM335X based boards |
| 11 | * |
| 12 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 16 | #include <env.h> |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 17 | #include <errno.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 18 | #include <init.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 19 | #include <malloc.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 20 | #include <net.h> |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 21 | #include <spl.h> |
| 22 | #include <asm/arch/cpu.h> |
| 23 | #include <asm/arch/hardware.h> |
| 24 | #include <asm/arch/omap.h> |
| 25 | #include <asm/arch/ddr_defs.h> |
| 26 | #include <asm/arch/clock.h> |
| 27 | #include <asm/arch/gpio.h> |
| 28 | #include <asm/arch/mmc_host_def.h> |
| 29 | #include <asm/arch/sys_proto.h> |
| 30 | #include "../../../drivers/video/da8xx-fb.h" |
| 31 | #include <asm/io.h> |
| 32 | #include <asm/emif.h> |
| 33 | #include <asm/gpio.h> |
| 34 | #include <i2c.h> |
| 35 | #include <miiphy.h> |
| 36 | #include <cpsw.h> |
| 37 | #include <watchdog.h> |
| 38 | #include "board.h" |
| 39 | #include "../common/factoryset.h" |
| 40 | #include "pmic.h" |
| 41 | #include <nand.h> |
| 42 | #include <bmp_layout.h> |
| 43 | |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 44 | #ifdef CONFIG_SPL_BUILD |
| 45 | static void board_init_ddr(void) |
| 46 | { |
| 47 | struct emif_regs pxm2_ddr3_emif_reg_data = { |
| 48 | .sdram_config = 0x41805332, |
| 49 | .sdram_tim1 = 0x666b3c9, |
| 50 | .sdram_tim2 = 0x243631ca, |
| 51 | .sdram_tim3 = 0x33f, |
| 52 | .emif_ddr_phy_ctlr_1 = 0x100005, |
| 53 | .zq_config = 0, |
| 54 | .ref_ctrl = 0x81a, |
| 55 | }; |
| 56 | |
| 57 | struct ddr_data pxm2_ddr3_data = { |
| 58 | .datardsratio0 = 0x81204812, |
| 59 | .datawdsratio0 = 0, |
| 60 | .datafwsratio0 = 0x8020080, |
| 61 | .datawrsratio0 = 0x4010040, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 62 | }; |
| 63 | |
| 64 | struct cmd_control pxm2_ddr3_cmd_ctrl_data = { |
| 65 | .cmd0csratio = 0x80, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 66 | .cmd0iclkout = 0, |
| 67 | .cmd1csratio = 0x80, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 68 | .cmd1iclkout = 0, |
| 69 | .cmd2csratio = 0x80, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 70 | .cmd2iclkout = 0, |
| 71 | }; |
| 72 | |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 73 | const struct ctrl_ioregs ioregs = { |
Egli, Samuel | 121636f | 2014-04-24 17:57:52 +0200 | [diff] [blame] | 74 | .cm0ioctl = DDR_IOCTRL_VAL, |
| 75 | .cm1ioctl = DDR_IOCTRL_VAL, |
| 76 | .cm2ioctl = DDR_IOCTRL_VAL, |
| 77 | .dt0ioctl = DDR_IOCTRL_VAL, |
| 78 | .dt1ioctl = DDR_IOCTRL_VAL, |
Lokesh Vutla | 303b267 | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 82 | &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); |
| 83 | } |
| 84 | |
| 85 | /* |
| 86 | * voltage switching for MPU frequency switching. |
| 87 | * @module = mpu - 0, core - 1 |
| 88 | * @vddx_op_vol_sel = vdd voltage to set |
| 89 | */ |
| 90 | |
| 91 | #define MPU 0 |
| 92 | #define CORE 1 |
| 93 | |
| 94 | int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) |
| 95 | { |
| 96 | uchar buf[4]; |
| 97 | unsigned int reg_offset; |
| 98 | |
| 99 | if (module == MPU) |
| 100 | reg_offset = PMIC_VDD1_OP_REG; |
| 101 | else |
| 102 | reg_offset = PMIC_VDD2_OP_REG; |
| 103 | |
| 104 | /* Select VDDx OP */ |
| 105 | if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 106 | return 1; |
| 107 | |
| 108 | buf[0] &= ~PMIC_OP_REG_CMD_MASK; |
| 109 | |
| 110 | if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 111 | return 1; |
| 112 | |
| 113 | /* Configure VDDx OP Voltage */ |
| 114 | if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 115 | return 1; |
| 116 | |
| 117 | buf[0] &= ~PMIC_OP_REG_SEL_MASK; |
| 118 | buf[0] |= vddx_op_vol_sel; |
| 119 | |
| 120 | if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 121 | return 1; |
| 122 | |
| 123 | if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) |
| 124 | return 1; |
| 125 | |
| 126 | if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel) |
| 127 | return 1; |
| 128 | |
| 129 | return 0; |
| 130 | } |
| 131 | |
| 132 | #define OSC (V_OSCK/1000000) |
| 133 | |
| 134 | const struct dpll_params dpll_mpu_pxm2 = { |
| 135 | 720, OSC-1, 1, -1, -1, -1, -1}; |
| 136 | |
| 137 | void spl_siemens_board_init(void) |
| 138 | { |
| 139 | uchar buf[4]; |
| 140 | /* |
| 141 | * pxm2 PMIC code. All boards currently want an MPU voltage |
| 142 | * of 1.2625V and CORE voltage of 1.1375V to operate at |
| 143 | * 720MHz. |
| 144 | */ |
| 145 | if (i2c_probe(PMIC_CTRL_I2C_ADDR)) |
| 146 | return; |
| 147 | |
| 148 | /* VDD1/2 voltage selection register access by control i/f */ |
| 149 | if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) |
| 150 | return; |
| 151 | |
| 152 | buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; |
| 153 | |
| 154 | if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) |
| 155 | return; |
| 156 | |
| 157 | /* Frequency switching for OPP 120 */ |
| 158 | if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || |
| 159 | voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { |
| 160 | printf("voltage update failed\n"); |
| 161 | } |
| 162 | } |
| 163 | #endif /* if def CONFIG_SPL_BUILD */ |
| 164 | |
| 165 | int read_eeprom(void) |
| 166 | { |
| 167 | /* nothing ToDo here for this board */ |
| 168 | |
| 169 | return 0; |
| 170 | } |
| 171 | |
| 172 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
| 173 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
| 174 | static void cpsw_control(int enabled) |
| 175 | { |
| 176 | /* VTP can be added here */ |
| 177 | |
| 178 | return; |
| 179 | } |
| 180 | |
| 181 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 182 | { |
| 183 | .slave_reg_ofs = 0x208, |
| 184 | .sliver_reg_ofs = 0xd80, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 185 | .phy_addr = 0, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 186 | .phy_if = PHY_INTERFACE_MODE_RMII, |
| 187 | }, |
| 188 | { |
| 189 | .slave_reg_ofs = 0x308, |
| 190 | .sliver_reg_ofs = 0xdc0, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 191 | .phy_addr = 1, |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 192 | .phy_if = PHY_INTERFACE_MODE_RMII, |
| 193 | }, |
| 194 | }; |
| 195 | |
| 196 | static struct cpsw_platform_data cpsw_data = { |
| 197 | .mdio_base = CPSW_MDIO_BASE, |
| 198 | .cpsw_base = CPSW_BASE, |
| 199 | .mdio_div = 0xff, |
| 200 | .channels = 4, |
| 201 | .cpdma_reg_ofs = 0x800, |
| 202 | .slaves = 1, |
| 203 | .slave_data = cpsw_slaves, |
| 204 | .ale_reg_ofs = 0xd00, |
| 205 | .ale_entries = 1024, |
| 206 | .host_port_reg_ofs = 0x108, |
| 207 | .hw_stats_reg_ofs = 0x900, |
| 208 | .bd_ram_ofs = 0x2000, |
| 209 | .mac_control = (1 << 5), |
| 210 | .control = cpsw_control, |
| 211 | .host_port_num = 0, |
| 212 | .version = CPSW_CTRL_VERSION_2, |
| 213 | }; |
| 214 | #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ |
| 215 | |
| 216 | #if defined(CONFIG_DRIVER_TI_CPSW) || \ |
Paul Kocialkowski | f34dfcb | 2015-08-04 17:04:06 +0200 | [diff] [blame] | 217 | (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 218 | int board_eth_init(bd_t *bis) |
| 219 | { |
| 220 | int n = 0; |
| 221 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
| 222 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
| 223 | struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 224 | #ifdef CONFIG_FACTORYSET |
| 225 | int rv; |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 226 | if (!is_valid_ethaddr(factory_dat.mac)) |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 227 | printf("Error: no valid mac address\n"); |
| 228 | else |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 229 | eth_env_set_enetaddr("ethaddr", factory_dat.mac); |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 230 | #endif /* #ifdef CONFIG_FACTORYSET */ |
| 231 | |
| 232 | /* Set rgmii mode and enable rmii clock to be sourced from chip */ |
Heiko Schocher | 9603afb | 2014-11-05 10:23:21 +0100 | [diff] [blame] | 233 | writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 234 | |
| 235 | rv = cpsw_register(&cpsw_data); |
| 236 | if (rv < 0) |
| 237 | printf("Error %d registering CPSW switch\n", rv); |
| 238 | else |
| 239 | n += rv; |
| 240 | #endif |
| 241 | return n; |
| 242 | } |
| 243 | #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ |
| 244 | |
| 245 | #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) |
| 246 | static struct da8xx_panel lcd_panels[] = { |
| 247 | /* AUO G156XW01 V1 */ |
| 248 | [0] = { |
| 249 | .name = "AUO_G156XW01_V1", |
| 250 | .width = 1376, |
| 251 | .height = 768, |
| 252 | .hfp = 14, |
| 253 | .hbp = 64, |
| 254 | .hsw = 56, |
| 255 | .vfp = 1, |
| 256 | .vbp = 28, |
| 257 | .vsw = 3, |
| 258 | .pxl_clk = 60000000, |
| 259 | .invert_pxl_clk = 0, |
| 260 | }, |
| 261 | /* AUO B101EVN06 V0 */ |
| 262 | [1] = { |
| 263 | .name = "AUO_B101EVN06_V0", |
| 264 | .width = 1280, |
| 265 | .height = 800, |
| 266 | .hfp = 52, |
| 267 | .hbp = 84, |
| 268 | .hsw = 36, |
| 269 | .vfp = 3, |
| 270 | .vbp = 14, |
| 271 | .vsw = 6, |
| 272 | .pxl_clk = 60000000, |
| 273 | .invert_pxl_clk = 0, |
| 274 | }, |
| 275 | /* |
| 276 | * Settings from factoryset |
| 277 | * stored in EEPROM |
| 278 | */ |
| 279 | [2] = { |
| 280 | .name = "factoryset", |
| 281 | .width = 0, |
| 282 | .height = 0, |
| 283 | .hfp = 0, |
| 284 | .hbp = 0, |
| 285 | .hsw = 0, |
| 286 | .vfp = 0, |
| 287 | .vbp = 0, |
| 288 | .vsw = 0, |
| 289 | .pxl_clk = 60000000, |
| 290 | .invert_pxl_clk = 0, |
| 291 | }, |
| 292 | }; |
| 293 | |
| 294 | static const struct display_panel disp_panel = { |
| 295 | WVGA, |
| 296 | 32, |
| 297 | 16, |
| 298 | COLOR_ACTIVE, |
| 299 | }; |
| 300 | |
| 301 | static const struct lcd_ctrl_config lcd_cfg = { |
| 302 | &disp_panel, |
| 303 | .ac_bias = 255, |
| 304 | .ac_bias_intrpt = 0, |
| 305 | .dma_burst_sz = 16, |
| 306 | .bpp = 32, |
| 307 | .fdd = 0x80, |
| 308 | .tft_alt_mode = 0, |
| 309 | .stn_565_mode = 0, |
| 310 | .mono_8bit_mode = 0, |
| 311 | .invert_line_clock = 1, |
| 312 | .invert_frm_clock = 1, |
| 313 | .sync_edge = 0, |
| 314 | .sync_ctrl = 1, |
| 315 | .raster_order = 0, |
| 316 | }; |
| 317 | |
| 318 | static int set_gpio(int gpio, int state) |
| 319 | { |
| 320 | gpio_request(gpio, "temp"); |
| 321 | gpio_direction_output(gpio, state); |
| 322 | gpio_set_value(gpio, state); |
| 323 | gpio_free(gpio); |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | static int enable_backlight(void) |
| 328 | { |
| 329 | set_gpio(BOARD_LCD_POWER, 1); |
| 330 | set_gpio(BOARD_BACK_LIGHT, 1); |
| 331 | set_gpio(BOARD_TOUCH_POWER, 1); |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | static int enable_pwm(void) |
| 336 | { |
| 337 | struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE; |
| 338 | struct pwmss_ecap_regs *ecap; |
| 339 | int ticks = PWM_TICKS; |
| 340 | int duty = PWM_DUTY; |
| 341 | |
| 342 | ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE; |
| 343 | /* enable clock */ |
| 344 | setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN); |
| 345 | /* TimeStam Counter register */ |
| 346 | writel(0xdb9, &ecap->tsctr); |
| 347 | /* config period */ |
| 348 | writel(ticks - 1, &ecap->cap3); |
| 349 | writel(ticks - 1, &ecap->cap1); |
| 350 | setbits_le16(&ecap->ecctl2, |
| 351 | (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0)); |
| 352 | /* config duty */ |
| 353 | writel(duty, &ecap->cap2); |
| 354 | writel(duty, &ecap->cap4); |
| 355 | /* start */ |
| 356 | setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN); |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | static struct dpll_regs dpll_lcd_regs = { |
| 361 | .cm_clkmode_dpll = CM_WKUP + 0x98, |
| 362 | .cm_idlest_dpll = CM_WKUP + 0x48, |
| 363 | .cm_clksel_dpll = CM_WKUP + 0x54, |
| 364 | }; |
| 365 | |
| 366 | /* no console on this board */ |
| 367 | int board_cfb_skip(void) |
| 368 | { |
| 369 | return 1; |
| 370 | } |
| 371 | |
| 372 | #define PLL_GET_M(v) ((v >> 8) & 0x7ff) |
| 373 | #define PLL_GET_N(v) (v & 0x7f) |
| 374 | |
| 375 | static int get_clk(struct dpll_regs *dpll_regs) |
| 376 | { |
| 377 | unsigned int val; |
| 378 | unsigned int m, n; |
| 379 | int f = 0; |
| 380 | |
| 381 | val = readl(dpll_regs->cm_clksel_dpll); |
| 382 | m = PLL_GET_M(val); |
| 383 | n = PLL_GET_N(val); |
| 384 | f = (m * V_OSCK) / n; |
| 385 | |
| 386 | return f; |
| 387 | }; |
| 388 | |
| 389 | int clk_get(int clk) |
| 390 | { |
| 391 | return get_clk(&dpll_lcd_regs); |
| 392 | }; |
| 393 | |
| 394 | static int conf_disp_pll(int m, int n) |
| 395 | { |
| 396 | struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; |
| 397 | struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; |
| 398 | struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; |
| 399 | |
| 400 | u32 *const clk_domains[] = { |
| 401 | &cmper->lcdclkctrl, |
| 402 | 0 |
| 403 | }; |
| 404 | u32 *const clk_modules_explicit_en[] = { |
| 405 | &cmper->lcdclkctrl, |
| 406 | &cmper->lcdcclkstctrl, |
| 407 | &cmper->epwmss0clkctrl, |
| 408 | 0 |
| 409 | }; |
| 410 | do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); |
| 411 | writel(0x0, &cmdpll->clklcdcpixelclk); |
| 412 | |
| 413 | do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); |
| 414 | |
| 415 | return 0; |
| 416 | } |
| 417 | |
| 418 | static int board_video_init(void) |
| 419 | { |
Samuel Egli | 8069bfe | 2013-11-04 14:05:03 +0100 | [diff] [blame] | 420 | conf_disp_pll(24, 1); |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 421 | if (factory_dat.pxm50) |
| 422 | da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); |
| 423 | else |
| 424 | da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); |
| 425 | |
| 426 | enable_pwm(); |
| 427 | enable_backlight(); |
| 428 | |
| 429 | return 0; |
| 430 | } |
| 431 | #endif |
Heiko Schocher | faf2dc6 | 2014-11-18 11:51:06 +0100 | [diff] [blame] | 432 | |
| 433 | #ifdef CONFIG_BOARD_LATE_INIT |
| 434 | int board_late_init(void) |
| 435 | { |
| 436 | int ret; |
| 437 | |
| 438 | omap_nand_switch_ecc(1, 8); |
| 439 | |
| 440 | #ifdef CONFIG_FACTORYSET |
| 441 | if (factory_dat.asn[0] != 0) { |
| 442 | char tmp[2 * MAX_STRING_LENGTH + 2]; |
| 443 | |
| 444 | if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0) |
| 445 | factory_dat.pxm50 = 1; |
| 446 | else |
| 447 | factory_dat.pxm50 = 0; |
| 448 | sprintf(tmp, "%s_%s", factory_dat.asn, |
| 449 | factory_dat.comp_version); |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 450 | ret = env_set("boardid", tmp); |
Heiko Schocher | faf2dc6 | 2014-11-18 11:51:06 +0100 | [diff] [blame] | 451 | if (ret) |
| 452 | printf("error setting board id\n"); |
| 453 | } else { |
| 454 | factory_dat.pxm50 = 1; |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 455 | ret = env_set("boardid", "PXM50_1.0"); |
Heiko Schocher | faf2dc6 | 2014-11-18 11:51:06 +0100 | [diff] [blame] | 456 | if (ret) |
| 457 | printf("error setting board id\n"); |
| 458 | } |
| 459 | debug("PXM50: %d\n", factory_dat.pxm50); |
| 460 | #endif |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | #endif |
| 465 | |
Heiko Schocher | 499c498 | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 466 | #include "../common/board.c" |