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Sumit Garg89a8ec92022-07-12 12:42:12 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Qualcomm QCS404 based evaluation board device tree source
4 *
5 * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
6 */
7
8/dts-v1/;
9
10#include "skeleton64.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
13#include <dt-bindings/clock/qcom,gcc-qcs404.h>
14
15/ {
16 model = "Qualcomm Technologies, Inc. QCS404 EVB";
17 compatible = "qcom,qcs404-evb", "qcom,qcs404";
18 #address-cells = <0x2>;
19 #size-cells = <0x2>;
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24
25 aliases {
26 serial0 = &debug_uart;
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0 0x80000000 0 0x40000000>;
32 };
33
34 soc {
35 #address-cells = <0x1>;
36 #size-cells = <0x1>;
37 ranges = <0x0 0x0 0x0 0xffffffff>;
38 compatible = "simple-bus";
39
40 pinctrl_north@1300000 {
Sumit Gargb7572e52022-07-27 13:52:04 +053041 compatible = "qcom,qcs404-pinctrl";
Sumit Garg89a8ec92022-07-12 12:42:12 +053042 reg = <0x1300000 0x200000>;
Sumit Garg8ed952d2023-02-01 19:28:49 +053043 gpio-controller;
44 gpio-count = <120>;
45 gpio-bank-name="soc";
46 #gpio-cells = <2>;
Sumit Garg89a8ec92022-07-12 12:42:12 +053047
48 blsp1_uart2: uart {
49 pins = "GPIO_17", "GPIO_18";
50 function = "blsp_uart2";
51 };
52 };
53
54 gcc: clock-controller@1800000 {
55 compatible = "qcom,gcc-qcs404";
56 reg = <0x1800000 0x80000>;
57 #address-cells = <0x1>;
58 #size-cells = <0x0>;
Sumit Gargd15d6702022-08-04 19:57:16 +053059 #clock-cells = <1>;
Sumit Garg89a8ec92022-07-12 12:42:12 +053060 };
61
Sumit Gargdc160a72022-08-04 19:57:13 +053062 reset: gcc-reset@1800000 {
63 compatible = "qcom,gcc-reset-qcs404";
64 reg = <0x1800000 0x80000>;
65 #reset-cells = <1>;
66 };
67
Sumit Garg89a8ec92022-07-12 12:42:12 +053068 debug_uart: serial@78b1000 {
69 compatible = "qcom,msm-uartdm-v1.4";
70 reg = <0x78b1000 0x200>;
71 clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
72 <&gcc GCC_BLSP1_AHB_CLK>;
73 bit-rate = <0xFF>;
74 pinctrl-names = "uart";
75 pinctrl-0 = <&blsp1_uart2>;
76 };
77
78 sdhci@7804000 {
79 compatible = "qcom,sdhci-msm-v5";
80 reg = <0x7804000 0x1000 0x7805000 0x1000>;
81 clock = <&gcc GCC_SDCC1_APPS_CLK>,
82 <&gcc GCC_SDCC1_AHB_CLK>;
83 bus-width = <0x8>;
84 index = <0x0>;
85 non-removable;
86 mmc-ddr-1_8v;
87 mmc-hs400-1_8v;
88 };
Sumit Gargd15d6702022-08-04 19:57:16 +053089
90 usb3_phy: phy@78000 {
91 compatible = "qcom,usb-ss-28nm-phy";
92 #phy-cells = <0>;
93 reg = <0x78000 0x400>;
94 clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
95 <&gcc GCC_USB3_PHY_PIPE_CLK>;
96 clock-names = "ahb", "pipe";
97 resets = <&reset GCC_USB3_PHY_BCR>,
98 <&reset GCC_USB3PHY_PHY_BCR>;
99 reset-names = "com", "phy";
100 };
101
102 usb2_phy_prim: phy@7a000 {
103 compatible = "qcom,usb-hs-28nm-femtophy";
104 #phy-cells = <0>;
105 reg = <0x7a000 0x200>;
106 clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
107 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
108 clock-names = "ahb", "sleep";
109 resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
110 <&reset GCC_USB2A_PHY_BCR>;
111 reset-names = "phy", "por";
112 };
113
114 usb2_phy_sec: phy@7c000 {
115 compatible = "qcom,usb-hs-28nm-femtophy";
116 #phy-cells = <0>;
117 reg = <0x7c000 0x200>;
118 clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
119 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
120 clock-names = "ahb", "sleep";
121 resets = <&reset GCC_QUSB2_PHY_BCR>,
122 <&reset GCC_USB2_HS_PHY_ONLY_BCR>;
123 reset-names = "phy", "por";
124 };
125
126 usb3: usb@7678800 {
127 compatible = "qcom,dwc3";
128 reg = <0x7678800 0x400>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges;
132 clocks = <&gcc GCC_USB30_MASTER_CLK>,
133 <&gcc GCC_SYS_NOC_USB3_CLK>,
134 <&gcc GCC_USB30_SLEEP_CLK>,
135 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
136 clock-names = "core", "iface", "sleep", "mock_utmi";
137
138 dwc3@7580000 {
139 compatible = "snps,dwc3";
140 reg = <0x7580000 0xcd00>;
141 phys = <&usb2_phy_prim>, <&usb3_phy>;
142 phy-names = "usb2-phy", "usb3-phy";
143 dr_mode = "host";
144 snps,has-lpm-erratum;
145 snps,hird-threshold = /bits/ 8 <0x10>;
146 snps,usb3_lpm_capable;
147 maximum-speed = "super-speed";
148 };
149 };
150
151 usb2: usb@79b8800 {
152 compatible = "qcom,dwc3";
153 reg = <0x79b8800 0x400>;
154 #address-cells = <1>;
155 #size-cells = <1>;
156 ranges;
157 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
158 <&gcc GCC_PCNOC_USB2_CLK>,
159 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
160 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
161 clock-names = "core", "iface", "sleep", "mock_utmi";
162
163 dwc3@78c0000 {
164 compatible = "snps,dwc3";
165 reg = <0x78c0000 0xcc00>;
166 phys = <&usb2_phy_sec>;
167 phy-names = "usb2-phy";
168 dr_mode = "peripheral";
169 snps,has-lpm-erratum;
170 snps,hird-threshold = /bits/ 8 <0x10>;
171 snps,usb3_lpm_capable;
172 maximum-speed = "high-speed";
173 };
174 };
Sumit Gargd04a52e2022-08-04 19:57:19 +0530175
176 spmi@200f000 {
177 compatible = "qcom,spmi-pmic-arb";
178 reg = <0x200f000 0x1000
179 0x2400000 0x400000
180 0x2c00000 0x400000>;
181 #address-cells = <0x1>;
182 #size-cells = <0x1>;
183
184 pms405_0: pms405@0 {
185 compatible = "qcom,spmi-pmic";
186 reg = <0x0 0x1>;
187 #address-cells = <0x1>;
188 #size-cells = <0x1>;
189
190 pms405_gpios: pms405_gpios@c000 {
191 compatible = "qcom,pms405-gpio";
192 reg = <0xc000 0x400>;
193 gpio-controller;
194 gpio-count = <12>;
195 #gpio-cells = <2>;
196 gpio-bank-name="pmic";
197 };
198 };
199 };
Sumit Garg89a8ec92022-07-12 12:42:12 +0530200 };
201};
202
203#include "qcs404-evb-uboot.dtsi"