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git01.mediatek.com / filogic / uboot / d15d670f8955b8c418d85bc72f65a68dec633c44 / . / arch / arm / dts / qcs404-evb.dts
blob: 719e6a25fb0822369eed0dacfee60ed63690b916 [file] [log] [blame]
Sumit Garg89a8ec92022-07-12 12:42:12 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Qualcomm QCS404 based evaluation board device tree source
4 *
5 * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
6 */
7
8/dts-v1/;
9
10#include "skeleton64.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
13#include <dt-bindings/clock/qcom,gcc-qcs404.h>
14
15/ {
16 model = "Qualcomm Technologies, Inc. QCS404 EVB";
17 compatible = "qcom,qcs404-evb", "qcom,qcs404";
18 #address-cells = <0x2>;
19 #size-cells = <0x2>;
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24
25 aliases {
26 serial0 = &debug_uart;
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0 0x80000000 0 0x40000000>;
32 };
33
34 soc {
35 #address-cells = <0x1>;
36 #size-cells = <0x1>;
37 ranges = <0x0 0x0 0x0 0xffffffff>;
38 compatible = "simple-bus";
39
40 pinctrl_north@1300000 {
41 compatible = "qcom,tlmm-qcs404";
42 reg = <0x1300000 0x200000>;
43
44 blsp1_uart2: uart {
45 pins = "GPIO_17", "GPIO_18";
46 function = "blsp_uart2";
47 };
48 };
49
50 gcc: clock-controller@1800000 {
51 compatible = "qcom,gcc-qcs404";
52 reg = <0x1800000 0x80000>;
53 #address-cells = <0x1>;
54 #size-cells = <0x0>;
Sumit Gargd15d6702022-08-04 19:57:16 +0530[diff] [blame^]55 #clock-cells = <1>;
Sumit Garg89a8ec92022-07-12 12:42:12 +0530[diff] [blame]56 };
57
Sumit Gargdc160a72022-08-04 19:57:13 +0530[diff] [blame]58 reset: gcc-reset@1800000 {
59 compatible = "qcom,gcc-reset-qcs404";
60 reg = <0x1800000 0x80000>;
61 #reset-cells = <1>;
62 };
63
Sumit Garg89a8ec92022-07-12 12:42:12 +0530[diff] [blame]64 debug_uart: serial@78b1000 {
65 compatible = "qcom,msm-uartdm-v1.4";
66 reg = <0x78b1000 0x200>;
67 clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
68 <&gcc GCC_BLSP1_AHB_CLK>;
69 bit-rate = <0xFF>;
70 pinctrl-names = "uart";
71 pinctrl-0 = <&blsp1_uart2>;
72 };
73
74 sdhci@7804000 {
75 compatible = "qcom,sdhci-msm-v5";
76 reg = <0x7804000 0x1000 0x7805000 0x1000>;
77 clock = <&gcc GCC_SDCC1_APPS_CLK>,
78 <&gcc GCC_SDCC1_AHB_CLK>;
79 bus-width = <0x8>;
80 index = <0x0>;
81 non-removable;
82 mmc-ddr-1_8v;
83 mmc-hs400-1_8v;
84 };
Sumit Gargd15d6702022-08-04 19:57:16 +0530[diff] [blame^]85
86 usb3_phy: phy@78000 {
87 compatible = "qcom,usb-ss-28nm-phy";
88 #phy-cells = <0>;
89 reg = <0x78000 0x400>;
90 clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
91 <&gcc GCC_USB3_PHY_PIPE_CLK>;
92 clock-names = "ahb", "pipe";
93 resets = <&reset GCC_USB3_PHY_BCR>,
94 <&reset GCC_USB3PHY_PHY_BCR>;
95 reset-names = "com", "phy";
96 };
97
98 usb2_phy_prim: phy@7a000 {
99 compatible = "qcom,usb-hs-28nm-femtophy";
100 #phy-cells = <0>;
101 reg = <0x7a000 0x200>;
102 clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
103 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
104 clock-names = "ahb", "sleep";
105 resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
106 <&reset GCC_USB2A_PHY_BCR>;
107 reset-names = "phy", "por";
108 };
109
110 usb2_phy_sec: phy@7c000 {
111 compatible = "qcom,usb-hs-28nm-femtophy";
112 #phy-cells = <0>;
113 reg = <0x7c000 0x200>;
114 clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
115 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
116 clock-names = "ahb", "sleep";
117 resets = <&reset GCC_QUSB2_PHY_BCR>,
118 <&reset GCC_USB2_HS_PHY_ONLY_BCR>;
119 reset-names = "phy", "por";
120 };
121
122 usb3: usb@7678800 {
123 compatible = "qcom,dwc3";
124 reg = <0x7678800 0x400>;
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges;
128 clocks = <&gcc GCC_USB30_MASTER_CLK>,
129 <&gcc GCC_SYS_NOC_USB3_CLK>,
130 <&gcc GCC_USB30_SLEEP_CLK>,
131 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
132 clock-names = "core", "iface", "sleep", "mock_utmi";
133
134 dwc3@7580000 {
135 compatible = "snps,dwc3";
136 reg = <0x7580000 0xcd00>;
137 phys = <&usb2_phy_prim>, <&usb3_phy>;
138 phy-names = "usb2-phy", "usb3-phy";
139 dr_mode = "host";
140 snps,has-lpm-erratum;
141 snps,hird-threshold = /bits/ 8 <0x10>;
142 snps,usb3_lpm_capable;
143 maximum-speed = "super-speed";
144 };
145 };
146
147 usb2: usb@79b8800 {
148 compatible = "qcom,dwc3";
149 reg = <0x79b8800 0x400>;
150 #address-cells = <1>;
151 #size-cells = <1>;
152 ranges;
153 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
154 <&gcc GCC_PCNOC_USB2_CLK>,
155 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
156 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
157 clock-names = "core", "iface", "sleep", "mock_utmi";
158
159 dwc3@78c0000 {
160 compatible = "snps,dwc3";
161 reg = <0x78c0000 0xcc00>;
162 phys = <&usb2_phy_sec>;
163 phy-names = "usb2-phy";
164 dr_mode = "peripheral";
165 snps,has-lpm-erratum;
166 snps,hird-threshold = /bits/ 8 <0x10>;
167 snps,usb3_lpm_capable;
168 maximum-speed = "high-speed";
169 };
170 };
Sumit Garg89a8ec92022-07-12 12:42:12 +0530[diff] [blame]171 };
172};
173
174#include "qcs404-evb-uboot.dtsi"