blob: db5d7b8834f1cbd5168952cfd1b5cc2b2db8a369 [file] [log] [blame]
Lokesh Vutla1a9dd212019-06-13 10:29:49 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board specific initialization for J721E EVM
4 *
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 *
8 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <spl.h>
Suman Anna8eac9e62019-06-13 10:29:50 +053013#include <asm/arch/sys_proto.h>
Lokesh Vutla1a9dd212019-06-13 10:29:49 +053014
15DECLARE_GLOBAL_DATA_PTR;
16
17int board_init(void)
18{
19 return 0;
20}
21
22int dram_init(void)
23{
24#ifdef CONFIG_PHYS_64BIT
25 gd->ram_size = 0x100000000;
26#else
27 gd->ram_size = 0x80000000;
28#endif
29
30 return 0;
31}
32
33ulong board_get_usable_ram_top(ulong total_size)
34{
35#ifdef CONFIG_PHYS_64BIT
36 /* Limit RAM used by U-Boot to the DDR low region */
37 if (gd->ram_top > 0x100000000)
38 return 0x100000000;
39#endif
40
41 return gd->ram_top;
42}
43
44int dram_init_banksize(void)
45{
46 /* Bank 0 declares the memory available in the DDR low region */
47 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
48 gd->bd->bi_dram[0].size = 0x80000000;
49 gd->ram_size = 0x80000000;
50
51#ifdef CONFIG_PHYS_64BIT
52 /* Bank 1 declares the memory available in the DDR high region */
53 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
54 gd->bd->bi_dram[1].size = 0x80000000;
55 gd->ram_size = 0x100000000;
56#endif
57
58 return 0;
59}
60
61#ifdef CONFIG_SPL_LOAD_FIT
62int board_fit_config_name_match(const char *name)
63{
64 if (!strcmp(name, "k3-j721e-common-proc-board"))
65 return 0;
66
67 return -1;
68}
69#endif
Suman Anna8eac9e62019-06-13 10:29:50 +053070
71#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
72int ft_board_setup(void *blob, bd_t *bd)
73{
74 int ret;
75
76 ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000");
77 if (ret)
78 printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
79
80 return ret;
81}
82#endif