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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
wdenk525d7b62005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local functions */
Michal Simeka888af72013-04-26 13:10:07 +020017static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000018
19/* Local defines */
Michal Simek20d6b952017-01-06 11:20:54 +010020enum {
21 FPGA_NONE = -1,
22 FPGA_INFO,
23 FPGA_LOAD,
24 FPGA_LOADB,
25 FPGA_DUMP,
26 FPGA_LOADMK,
27 FPGA_LOADP,
28 FPGA_LOADBP,
29 FPGA_LOADFS,
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053030 FPGA_LOADS,
Michal Simek20d6b952017-01-06 11:20:54 +010031};
wdenk4a9cbbe2002-08-27 09:48:53 +000032
33/* ------------------------------------------------------------------------- */
34/* command form:
35 * fpga <op> <device number> <data addr> <datasize>
36 * where op is 'load', 'dump', or 'info'
37 * If there is no device number field, the fpga environment variable is used.
38 * If there is no data addr field, the fpgadata environment variable is used.
39 * The info command requires no data address field.
40 */
Michal Simeka888af72013-04-26 13:10:07 +020041int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000042{
wdenk1ebf41e2004-01-02 14:00:00 +000043 int op, dev = FPGA_INVALID_DEVICE;
44 size_t data_size = 0;
45 void *fpga_data = NULL;
Simon Glass64b723f2017-08-03 12:22:12 -060046 char *devstr = env_get("fpga");
47 char *datastr = env_get("fpgadata");
wdenk1ebf41e2004-01-02 14:00:00 +000048 int rc = FPGA_FAIL;
Stefano Babic67d7f562010-10-19 09:22:52 +020049 int wrong_parms = 0;
Michal Simeka888af72013-04-26 13:10:07 +020050#if defined(CONFIG_FIT)
Marian Balakowiczd79162d2008-03-12 10:33:01 +010051 const char *fit_uname = NULL;
52 ulong fit_addr;
53#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053054#if defined(CONFIG_CMD_FPGA_LOADFS)
55 fpga_fs_info fpga_fsinfo;
56 fpga_fsinfo.fstype = FS_TYPE_ANY;
57#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053058#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
59 struct fpga_secure_info fpga_sec_info;
60
61 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
62#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000063
wdenk1ebf41e2004-01-02 14:00:00 +000064 if (devstr)
Michal Simeka888af72013-04-26 13:10:07 +020065 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenk1ebf41e2004-01-02 14:00:00 +000066 if (datastr)
Michal Simeka888af72013-04-26 13:10:07 +020067 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000068
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053069 if (argc > 9 || argc < 2) {
70 debug("%s: Too many or too few args (%d)\n", __func__, argc);
71 return CMD_RET_USAGE;
72 }
73
74 op = (int)fpga_get_op(argv[1]);
75
76 switch (op) {
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053077#if defined(CONFIG_CMD_FPGA_LOADFS)
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053078 case FPGA_LOADFS:
79 if (argc < 9)
80 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053081 fpga_fsinfo.blocksize = (unsigned int)
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053082 simple_strtoul(argv[5], NULL, 16);
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053083 fpga_fsinfo.interface = argv[6];
84 fpga_fsinfo.dev_part = argv[7];
85 fpga_fsinfo.filename = argv[8];
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053086 argc = 5;
87 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053088#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053089#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
90 case FPGA_LOADS:
91 if (argc < 7)
92 return CMD_RET_USAGE;
93 if (argc == 8)
94 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
95 simple_strtoull(argv[7],
96 NULL, 16);
97 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
98 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
99 argc = 5;
100 break;
101#endif
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +0530102 default:
103 break;
104 }
105
106 switch (argc) {
wdenk1ebf41e2004-01-02 14:00:00 +0000107 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simeka888af72013-04-26 13:10:07 +0200108 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100109
wdenk1ebf41e2004-01-02 14:00:00 +0000110 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100111#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200112 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
113 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100114 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +0200115 debug("* fpga: subimage '%s' from FIT image ",
116 fit_uname);
117 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100118 } else
119#endif
120 {
Michal Simeka888af72013-04-26 13:10:07 +0200121 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +0000122 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simeka888af72013-04-26 13:10:07 +0200123 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100124 }
Michal Simek77bb86d2016-01-05 13:51:48 +0100125 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100126
wdenk1ebf41e2004-01-02 14:00:00 +0000127 case 3: /* fpga <op> <dev | data addr> */
Michal Simeka888af72013-04-26 13:10:07 +0200128 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +0000129 debug("%s: device = %d\n", __func__, dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000130 /* FIXME - this is a really weak test */
Michal Simeka888af72013-04-26 13:10:07 +0200131 if ((argc == 3) && (dev > fpga_count())) {
132 /* must be buffer ptr */
Stefano Babicb69b9a52011-12-28 06:47:01 +0000133 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simeka888af72013-04-26 13:10:07 +0200134 __func__);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100135
136#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200137 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
138 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100139 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +0200140 debug("* fpga: subimage '%s' from FIT image ",
141 fit_uname);
142 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100143 } else
144#endif
145 {
Michal Simek77bb86d2016-01-05 13:51:48 +0100146 fpga_data = (void *)(uintptr_t)dev;
Michal Simeka888af72013-04-26 13:10:07 +0200147 debug("* fpga: cmdline image addr = 0x%08lx\n",
148 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100149 }
150
Michal Simek77bb86d2016-01-05 13:51:48 +0100151 debug("%s: fpga_data = 0x%lx\n",
152 __func__, (ulong)fpga_data);
wdenk1ebf41e2004-01-02 14:00:00 +0000153 dev = FPGA_INVALID_DEVICE; /* reset device num */
154 }
wdenk1ebf41e2004-01-02 14:00:00 +0000155 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000156
Stefano Babic67d7f562010-10-19 09:22:52 +0200157 if (dev == FPGA_INVALID_DEVICE) {
158 puts("FPGA device not specified\n");
159 op = FPGA_NONE;
160 }
161
162 switch (op) {
163 case FPGA_NONE:
164 case FPGA_INFO:
165 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530166#if defined(CONFIG_CMD_FPGA_LOADFS)
167 case FPGA_LOADFS:
168 /* Blocksize can be zero */
169 if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
170 !fpga_fsinfo.filename)
171 wrong_parms = 1;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530172 break;
173#endif
174#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
175 case FPGA_LOADS:
176 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
177 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
178 puts("ERR: use <fpga load> for NonSecure bitstream\n");
179 wrong_parms = 1;
180 }
181
182 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
183 !fpga_sec_info.userkey_addr) {
184 wrong_parms = 1;
185 puts("ERR:User key not provided\n");
186 }
187 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530188#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200189 case FPGA_LOAD:
Michal Simek64c70982014-05-02 13:43:39 +0200190 case FPGA_LOADP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200191 case FPGA_LOADB:
Michal Simek64c70982014-05-02 13:43:39 +0200192 case FPGA_LOADBP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200193 case FPGA_DUMP:
194 if (!fpga_data || !data_size)
195 wrong_parms = 1;
196 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530197#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babic67d7f562010-10-19 09:22:52 +0200198 case FPGA_LOADMK:
199 if (!fpga_data)
200 wrong_parms = 1;
201 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530202#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200203 }
204
205 if (wrong_parms) {
206 puts("Wrong parameters for FPGA request\n");
207 op = FPGA_NONE;
208 }
209
wdenk1ebf41e2004-01-02 14:00:00 +0000210 switch (op) {
211 case FPGA_NONE:
Simon Glassa06dfc72011-12-10 08:44:01 +0000212 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000213
wdenk1ebf41e2004-01-02 14:00:00 +0000214 case FPGA_INFO:
Michal Simeka888af72013-04-26 13:10:07 +0200215 rc = fpga_info(dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000216 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000217
wdenk1ebf41e2004-01-02 14:00:00 +0000218 case FPGA_LOAD:
Michal Simek14663652014-05-02 14:09:30 +0200219 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenk1ebf41e2004-01-02 14:00:00 +0000220 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000221
Michal Simek64c70982014-05-02 13:43:39 +0200222#if defined(CONFIG_CMD_FPGA_LOADP)
223 case FPGA_LOADP:
224 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
225 break;
226#endif
227
wdenk310b4fc2005-01-09 18:12:51 +0000228 case FPGA_LOADB:
Michal Simek14663652014-05-02 14:09:30 +0200229 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk310b4fc2005-01-09 18:12:51 +0000230 break;
Michal Simek64c70982014-05-02 13:43:39 +0200231
232#if defined(CONFIG_CMD_FPGA_LOADBP)
233 case FPGA_LOADBP:
234 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
235 break;
236#endif
wdenk310b4fc2005-01-09 18:12:51 +0000237
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530238#if defined(CONFIG_CMD_FPGA_LOADFS)
239 case FPGA_LOADFS:
240 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
241 break;
242#endif
243
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530244#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
245 case FPGA_LOADS:
246 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
247 break;
248#endif
249
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530250#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200251 case FPGA_LOADMK:
Michal Simeka888af72013-04-26 13:10:07 +0200252 switch (genimg_get_format(fpga_data)) {
Heiko Schocher515eb122014-05-28 11:33:33 +0200253#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100254 case IMAGE_FORMAT_LEGACY:
255 {
Michal Simeka888af72013-04-26 13:10:07 +0200256 image_header_t *hdr =
257 (image_header_t *)fpga_data;
258 ulong data;
Michal Simekead2d422013-10-04 10:51:01 +0200259 uint8_t comp;
260
261 comp = image_get_comp(hdr);
262 if (comp == IH_COMP_GZIP) {
Michal Simekbe09b942014-07-16 10:30:50 +0200263#if defined(CONFIG_GZIP)
Michal Simekead2d422013-10-04 10:51:01 +0200264 ulong image_buf = image_get_data(hdr);
265 data = image_get_load(hdr);
266 ulong image_size = ~0UL;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200267
Michal Simekead2d422013-10-04 10:51:01 +0200268 if (gunzip((void *)data, ~0UL,
269 (void *)image_buf,
270 &image_size) != 0) {
271 puts("GUNZIP: error\n");
272 return 1;
273 }
274 data_size = image_size;
Michal Simekbe09b942014-07-16 10:30:50 +0200275#else
276 puts("Gunzip image is not supported\n");
277 return 1;
278#endif
Michal Simekead2d422013-10-04 10:51:01 +0200279 } else {
280 data = (ulong)image_get_data(hdr);
281 data_size = image_get_data_size(hdr);
282 }
Michal Simek14663652014-05-02 14:09:30 +0200283 rc = fpga_load(dev, (void *)data, data_size,
284 BIT_FULL);
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200285 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100286 break;
Heiko Schocher515eb122014-05-28 11:33:33 +0200287#endif
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100288#if defined(CONFIG_FIT)
289 case IMAGE_FORMAT_FIT:
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100290 {
291 const void *fit_hdr = (const void *)fpga_data;
292 int noffset;
Wolfgang Denk74f9b382011-07-30 13:33:49 +0000293 const void *fit_data;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100294
295 if (fit_uname == NULL) {
Michal Simeka888af72013-04-26 13:10:07 +0200296 puts("No FIT subimage unit name\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100297 return 1;
298 }
299
Michal Simeka888af72013-04-26 13:10:07 +0200300 if (!fit_check_format(fit_hdr)) {
301 puts("Bad FIT image format\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100302 return 1;
303 }
304
305 /* get fpga component image node offset */
Michal Simeka888af72013-04-26 13:10:07 +0200306 noffset = fit_image_get_node(fit_hdr,
307 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100308 if (noffset < 0) {
Michal Simeka888af72013-04-26 13:10:07 +0200309 printf("Can't find '%s' FIT subimage\n",
310 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100311 return 1;
312 }
313
314 /* verify integrity */
Simon Glass7428ad12013-05-07 06:11:57 +0000315 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100316 puts ("Bad Data Hash\n");
317 return 1;
318 }
319
320 /* get fpga subimage data address and length */
Michal Simeka888af72013-04-26 13:10:07 +0200321 if (fit_image_get_data(fit_hdr, noffset,
322 &fit_data, &data_size)) {
323 puts("Fpga subimage data not found\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100324 return 1;
325 }
326
Michal Simek14663652014-05-02 14:09:30 +0200327 rc = fpga_load(dev, fit_data, data_size,
328 BIT_FULL);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100329 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100330 break;
331#endif
332 default:
Michal Simeka888af72013-04-26 13:10:07 +0200333 puts("** Unknown image type\n");
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100334 rc = FPGA_FAIL;
335 break;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200336 }
337 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530338#endif
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200339
wdenk1ebf41e2004-01-02 14:00:00 +0000340 case FPGA_DUMP:
Michal Simeka888af72013-04-26 13:10:07 +0200341 rc = fpga_dump(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000342 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000343
wdenk1ebf41e2004-01-02 14:00:00 +0000344 default:
Michal Simeka888af72013-04-26 13:10:07 +0200345 printf("Unknown operation\n");
Simon Glassa06dfc72011-12-10 08:44:01 +0000346 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000347 }
Michal Simeka888af72013-04-26 13:10:07 +0200348 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000349}
350
wdenk4a9cbbe2002-08-27 09:48:53 +0000351/*
352 * Map op to supported operations. We don't use a table since we
353 * would just have to relocate it from flash anyway.
354 */
Michal Simeka888af72013-04-26 13:10:07 +0200355static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000356{
357 int op = FPGA_NONE;
358
Michal Simeka888af72013-04-26 13:10:07 +0200359 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000360 op = FPGA_INFO;
Michal Simeka888af72013-04-26 13:10:07 +0200361 else if (!strcmp("loadb", opstr))
wdenk310b4fc2005-01-09 18:12:51 +0000362 op = FPGA_LOADB;
Michal Simeka888af72013-04-26 13:10:07 +0200363 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000364 op = FPGA_LOAD;
Michal Simek64c70982014-05-02 13:43:39 +0200365#if defined(CONFIG_CMD_FPGA_LOADP)
366 else if (!strcmp("loadp", opstr))
367 op = FPGA_LOADP;
368#endif
369#if defined(CONFIG_CMD_FPGA_LOADBP)
370 else if (!strcmp("loadbp", opstr))
371 op = FPGA_LOADBP;
372#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530373#if defined(CONFIG_CMD_FPGA_LOADFS)
374 else if (!strcmp("loadfs", opstr))
375 op = FPGA_LOADFS;
376#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530377#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200378 else if (!strcmp("loadmk", opstr))
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200379 op = FPGA_LOADMK;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530380#endif
Michal Simeka888af72013-04-26 13:10:07 +0200381 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000382 op = FPGA_DUMP;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530383#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
384 else if (!strcmp("loads", opstr))
385 op = FPGA_LOADS;
386#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000387
Michal Simeka888af72013-04-26 13:10:07 +0200388 if (op == FPGA_NONE)
389 printf("Unknown fpga operation \"%s\"\n", opstr);
390
wdenk4a9cbbe2002-08-27 09:48:53 +0000391 return op;
392}
393
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530394#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530395U_BOOT_CMD(fpga, 9, 1, do_fpga,
396#else
Michal Simeka888af72013-04-26 13:10:07 +0200397U_BOOT_CMD(fpga, 6, 1, do_fpga,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530398#endif
Michal Simeka888af72013-04-26 13:10:07 +0200399 "loadable FPGA image support",
400 "[operation type] [device number] [image address] [image size]\n"
401 "fpga operations:\n"
Michal Simek70da5922015-01-26 08:52:27 +0100402 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simeka888af72013-04-26 13:10:07 +0200403 " info\t[dev]\t\t\tlist known device information\n"
404 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200405#if defined(CONFIG_CMD_FPGA_LOADP)
406 " loadp\t[dev] [address] [size]\t"
407 "Load device from memory buffer with partial bitstream\n"
408#endif
Michal Simeka888af72013-04-26 13:10:07 +0200409 " loadb\t[dev] [address] [size]\t"
410 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200411#if defined(CONFIG_CMD_FPGA_LOADBP)
412 " loadbp\t[dev] [address] [size]\t"
413 "Load device from bitstream buffer with partial bitstream"
414 "(Xilinx only)\n"
415#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530416#if defined(CONFIG_CMD_FPGA_LOADFS)
417 "Load device from filesystem (FAT by default) (Xilinx only)\n"
418 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
419 " [<dev[:part]>] <filename>\n"
420#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530421#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200422 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100423#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200424 "\n"
425 "\tFor loadmk operating on FIT format uImage address must include\n"
426 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100427#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530428#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530429#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
430 "Load encrypted bitstream (Xilinx only)\n"
431 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
432 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
433 "Loads the secure bistreams(authenticated/encrypted/both\n"
434 "authenticated and encrypted) of [size] from [address].\n"
435 "The auth-OCM/DDR flag specifies to perform authentication\n"
436 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
437 "The enc flag specifies which key to be used for decryption\n"
438 "0-device key, 1-user key, 2-no encryption.\n"
439 "The optional Userkey address specifies from which address key\n"
440 "has to be used for decryption if user key is selected.\n"
441 "NOTE: the sceure bitstream has to be created using xilinx\n"
442 "bootgen tool only.\n"
443#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100444);