Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000, 2001 |
| 4 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * FPGA support |
| 9 | */ |
| 10 | #include <common.h> |
| 11 | #include <command.h> |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 12 | #include <fpga.h> |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 13 | #include <fs.h> |
wdenk | 525d7b6 | 2005-01-22 18:13:04 +0000 | [diff] [blame] | 14 | #include <malloc.h> |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 15 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 16 | /* Local functions */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 17 | static int fpga_get_op(char *opstr); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 18 | |
| 19 | /* Local defines */ |
Michal Simek | 20d6b95 | 2017-01-06 11:20:54 +0100 | [diff] [blame] | 20 | enum { |
| 21 | FPGA_NONE = -1, |
| 22 | FPGA_INFO, |
| 23 | FPGA_LOAD, |
| 24 | FPGA_LOADB, |
| 25 | FPGA_DUMP, |
| 26 | FPGA_LOADMK, |
| 27 | FPGA_LOADP, |
| 28 | FPGA_LOADBP, |
| 29 | FPGA_LOADFS, |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 30 | FPGA_LOADS, |
Michal Simek | 20d6b95 | 2017-01-06 11:20:54 +0100 | [diff] [blame] | 31 | }; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 32 | |
| 33 | /* ------------------------------------------------------------------------- */ |
| 34 | /* command form: |
| 35 | * fpga <op> <device number> <data addr> <datasize> |
| 36 | * where op is 'load', 'dump', or 'info' |
| 37 | * If there is no device number field, the fpga environment variable is used. |
| 38 | * If there is no data addr field, the fpgadata environment variable is used. |
| 39 | * The info command requires no data address field. |
| 40 | */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 41 | int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 42 | { |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 43 | int op, dev = FPGA_INVALID_DEVICE; |
| 44 | size_t data_size = 0; |
| 45 | void *fpga_data = NULL; |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 46 | char *devstr = env_get("fpga"); |
| 47 | char *datastr = env_get("fpgadata"); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 48 | int rc = FPGA_FAIL; |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 49 | int wrong_parms = 0; |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 50 | #if defined(CONFIG_FIT) |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 51 | const char *fit_uname = NULL; |
| 52 | ulong fit_addr; |
| 53 | #endif |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 54 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
| 55 | fpga_fs_info fpga_fsinfo; |
| 56 | fpga_fsinfo.fstype = FS_TYPE_ANY; |
| 57 | #endif |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 58 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 59 | struct fpga_secure_info fpga_sec_info; |
| 60 | |
| 61 | memset(&fpga_sec_info, 0, sizeof(fpga_sec_info)); |
| 62 | #endif |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 63 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 64 | if (devstr) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 65 | dev = (int) simple_strtoul(devstr, NULL, 16); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 66 | if (datastr) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 67 | fpga_data = (void *)simple_strtoul(datastr, NULL, 16); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 68 | |
Siva Durga Prasad Paladugu | 8f039b1 | 2018-05-31 15:10:21 +0530 | [diff] [blame] | 69 | if (argc > 9 || argc < 2) { |
| 70 | debug("%s: Too many or too few args (%d)\n", __func__, argc); |
| 71 | return CMD_RET_USAGE; |
| 72 | } |
| 73 | |
| 74 | op = (int)fpga_get_op(argv[1]); |
| 75 | |
| 76 | switch (op) { |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 77 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
Siva Durga Prasad Paladugu | 8f039b1 | 2018-05-31 15:10:21 +0530 | [diff] [blame] | 78 | case FPGA_LOADFS: |
| 79 | if (argc < 9) |
| 80 | return CMD_RET_USAGE; |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 81 | fpga_fsinfo.blocksize = (unsigned int) |
Siva Durga Prasad Paladugu | 8f039b1 | 2018-05-31 15:10:21 +0530 | [diff] [blame] | 82 | simple_strtoul(argv[5], NULL, 16); |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 83 | fpga_fsinfo.interface = argv[6]; |
| 84 | fpga_fsinfo.dev_part = argv[7]; |
| 85 | fpga_fsinfo.filename = argv[8]; |
Siva Durga Prasad Paladugu | 8f039b1 | 2018-05-31 15:10:21 +0530 | [diff] [blame] | 86 | argc = 5; |
| 87 | break; |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 88 | #endif |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 89 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 90 | case FPGA_LOADS: |
| 91 | if (argc < 7) |
| 92 | return CMD_RET_USAGE; |
| 93 | if (argc == 8) |
| 94 | fpga_sec_info.userkey_addr = (u8 *)(uintptr_t) |
| 95 | simple_strtoull(argv[7], |
| 96 | NULL, 16); |
| 97 | fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16); |
| 98 | fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16); |
| 99 | argc = 5; |
| 100 | break; |
| 101 | #endif |
Siva Durga Prasad Paladugu | 8f039b1 | 2018-05-31 15:10:21 +0530 | [diff] [blame] | 102 | default: |
| 103 | break; |
| 104 | } |
| 105 | |
| 106 | switch (argc) { |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 107 | case 5: /* fpga <op> <dev> <data> <datasize> */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 108 | data_size = simple_strtoul(argv[4], NULL, 16); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 109 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 110 | case 4: /* fpga <op> <dev> <data> */ |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 111 | #if defined(CONFIG_FIT) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 112 | if (fit_parse_subimage(argv[3], (ulong)fpga_data, |
| 113 | &fit_addr, &fit_uname)) { |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 114 | fpga_data = (void *)fit_addr; |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 115 | debug("* fpga: subimage '%s' from FIT image ", |
| 116 | fit_uname); |
| 117 | debug("at 0x%08lx\n", fit_addr); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 118 | } else |
| 119 | #endif |
| 120 | { |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 121 | fpga_data = (void *)simple_strtoul(argv[3], NULL, 16); |
Stefano Babic | b69b9a5 | 2011-12-28 06:47:01 +0000 | [diff] [blame] | 122 | debug("* fpga: cmdline image address = 0x%08lx\n", |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 123 | (ulong)fpga_data); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 124 | } |
Michal Simek | 77bb86d | 2016-01-05 13:51:48 +0100 | [diff] [blame] | 125 | debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 126 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 127 | case 3: /* fpga <op> <dev | data addr> */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 128 | dev = (int)simple_strtoul(argv[2], NULL, 16); |
Stefano Babic | b69b9a5 | 2011-12-28 06:47:01 +0000 | [diff] [blame] | 129 | debug("%s: device = %d\n", __func__, dev); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 130 | /* FIXME - this is a really weak test */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 131 | if ((argc == 3) && (dev > fpga_count())) { |
| 132 | /* must be buffer ptr */ |
Stefano Babic | b69b9a5 | 2011-12-28 06:47:01 +0000 | [diff] [blame] | 133 | debug("%s: Assuming buffer pointer in arg 3\n", |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 134 | __func__); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 135 | |
| 136 | #if defined(CONFIG_FIT) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 137 | if (fit_parse_subimage(argv[2], (ulong)fpga_data, |
| 138 | &fit_addr, &fit_uname)) { |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 139 | fpga_data = (void *)fit_addr; |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 140 | debug("* fpga: subimage '%s' from FIT image ", |
| 141 | fit_uname); |
| 142 | debug("at 0x%08lx\n", fit_addr); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 143 | } else |
| 144 | #endif |
| 145 | { |
Michal Simek | 77bb86d | 2016-01-05 13:51:48 +0100 | [diff] [blame] | 146 | fpga_data = (void *)(uintptr_t)dev; |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 147 | debug("* fpga: cmdline image addr = 0x%08lx\n", |
| 148 | (ulong)fpga_data); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 149 | } |
| 150 | |
Michal Simek | 77bb86d | 2016-01-05 13:51:48 +0100 | [diff] [blame] | 151 | debug("%s: fpga_data = 0x%lx\n", |
| 152 | __func__, (ulong)fpga_data); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 153 | dev = FPGA_INVALID_DEVICE; /* reset device num */ |
| 154 | } |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 155 | } |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 156 | |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 157 | if (dev == FPGA_INVALID_DEVICE) { |
| 158 | puts("FPGA device not specified\n"); |
| 159 | op = FPGA_NONE; |
| 160 | } |
| 161 | |
| 162 | switch (op) { |
| 163 | case FPGA_NONE: |
| 164 | case FPGA_INFO: |
| 165 | break; |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 166 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
| 167 | case FPGA_LOADFS: |
| 168 | /* Blocksize can be zero */ |
| 169 | if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part || |
| 170 | !fpga_fsinfo.filename) |
| 171 | wrong_parms = 1; |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 172 | break; |
| 173 | #endif |
| 174 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 175 | case FPGA_LOADS: |
| 176 | if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH && |
| 177 | fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) { |
| 178 | puts("ERR: use <fpga load> for NonSecure bitstream\n"); |
| 179 | wrong_parms = 1; |
| 180 | } |
| 181 | |
| 182 | if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY && |
| 183 | !fpga_sec_info.userkey_addr) { |
| 184 | wrong_parms = 1; |
| 185 | puts("ERR:User key not provided\n"); |
| 186 | } |
| 187 | break; |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 188 | #endif |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 189 | case FPGA_LOAD: |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 190 | case FPGA_LOADP: |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 191 | case FPGA_LOADB: |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 192 | case FPGA_LOADBP: |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 193 | case FPGA_DUMP: |
| 194 | if (!fpga_data || !data_size) |
| 195 | wrong_parms = 1; |
| 196 | break; |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 197 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 198 | case FPGA_LOADMK: |
| 199 | if (!fpga_data) |
| 200 | wrong_parms = 1; |
| 201 | break; |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 202 | #endif |
Stefano Babic | 67d7f56 | 2010-10-19 09:22:52 +0200 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | if (wrong_parms) { |
| 206 | puts("Wrong parameters for FPGA request\n"); |
| 207 | op = FPGA_NONE; |
| 208 | } |
| 209 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 210 | switch (op) { |
| 211 | case FPGA_NONE: |
Simon Glass | a06dfc7 | 2011-12-10 08:44:01 +0000 | [diff] [blame] | 212 | return CMD_RET_USAGE; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 213 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 214 | case FPGA_INFO: |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 215 | rc = fpga_info(dev); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 216 | break; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 217 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 218 | case FPGA_LOAD: |
Michal Simek | 1466365 | 2014-05-02 14:09:30 +0200 | [diff] [blame] | 219 | rc = fpga_load(dev, fpga_data, data_size, BIT_FULL); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 220 | break; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 221 | |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 222 | #if defined(CONFIG_CMD_FPGA_LOADP) |
| 223 | case FPGA_LOADP: |
| 224 | rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL); |
| 225 | break; |
| 226 | #endif |
| 227 | |
wdenk | 310b4fc | 2005-01-09 18:12:51 +0000 | [diff] [blame] | 228 | case FPGA_LOADB: |
Michal Simek | 1466365 | 2014-05-02 14:09:30 +0200 | [diff] [blame] | 229 | rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL); |
wdenk | 310b4fc | 2005-01-09 18:12:51 +0000 | [diff] [blame] | 230 | break; |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 231 | |
| 232 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
| 233 | case FPGA_LOADBP: |
| 234 | rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL); |
| 235 | break; |
| 236 | #endif |
wdenk | 310b4fc | 2005-01-09 18:12:51 +0000 | [diff] [blame] | 237 | |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 238 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
| 239 | case FPGA_LOADFS: |
| 240 | rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo); |
| 241 | break; |
| 242 | #endif |
| 243 | |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 244 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 245 | case FPGA_LOADS: |
| 246 | rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info); |
| 247 | break; |
| 248 | #endif |
| 249 | |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 250 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
Stefan Roese | 5f1cf2d | 2006-08-15 14:15:51 +0200 | [diff] [blame] | 251 | case FPGA_LOADMK: |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 252 | switch (genimg_get_format(fpga_data)) { |
Heiko Schocher | 515eb12 | 2014-05-28 11:33:33 +0200 | [diff] [blame] | 253 | #if defined(CONFIG_IMAGE_FORMAT_LEGACY) |
Marian Balakowicz | dbdd16a | 2008-02-04 08:28:09 +0100 | [diff] [blame] | 254 | case IMAGE_FORMAT_LEGACY: |
| 255 | { |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 256 | image_header_t *hdr = |
| 257 | (image_header_t *)fpga_data; |
| 258 | ulong data; |
Michal Simek | ead2d42 | 2013-10-04 10:51:01 +0200 | [diff] [blame] | 259 | uint8_t comp; |
| 260 | |
| 261 | comp = image_get_comp(hdr); |
| 262 | if (comp == IH_COMP_GZIP) { |
Michal Simek | be09b94 | 2014-07-16 10:30:50 +0200 | [diff] [blame] | 263 | #if defined(CONFIG_GZIP) |
Michal Simek | ead2d42 | 2013-10-04 10:51:01 +0200 | [diff] [blame] | 264 | ulong image_buf = image_get_data(hdr); |
| 265 | data = image_get_load(hdr); |
| 266 | ulong image_size = ~0UL; |
Stefan Roese | 5f1cf2d | 2006-08-15 14:15:51 +0200 | [diff] [blame] | 267 | |
Michal Simek | ead2d42 | 2013-10-04 10:51:01 +0200 | [diff] [blame] | 268 | if (gunzip((void *)data, ~0UL, |
| 269 | (void *)image_buf, |
| 270 | &image_size) != 0) { |
| 271 | puts("GUNZIP: error\n"); |
| 272 | return 1; |
| 273 | } |
| 274 | data_size = image_size; |
Michal Simek | be09b94 | 2014-07-16 10:30:50 +0200 | [diff] [blame] | 275 | #else |
| 276 | puts("Gunzip image is not supported\n"); |
| 277 | return 1; |
| 278 | #endif |
Michal Simek | ead2d42 | 2013-10-04 10:51:01 +0200 | [diff] [blame] | 279 | } else { |
| 280 | data = (ulong)image_get_data(hdr); |
| 281 | data_size = image_get_data_size(hdr); |
| 282 | } |
Michal Simek | 1466365 | 2014-05-02 14:09:30 +0200 | [diff] [blame] | 283 | rc = fpga_load(dev, (void *)data, data_size, |
| 284 | BIT_FULL); |
Stefan Roese | 5f1cf2d | 2006-08-15 14:15:51 +0200 | [diff] [blame] | 285 | } |
Marian Balakowicz | dbdd16a | 2008-02-04 08:28:09 +0100 | [diff] [blame] | 286 | break; |
Heiko Schocher | 515eb12 | 2014-05-28 11:33:33 +0200 | [diff] [blame] | 287 | #endif |
Marian Balakowicz | dbdd16a | 2008-02-04 08:28:09 +0100 | [diff] [blame] | 288 | #if defined(CONFIG_FIT) |
| 289 | case IMAGE_FORMAT_FIT: |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 290 | { |
| 291 | const void *fit_hdr = (const void *)fpga_data; |
| 292 | int noffset; |
Wolfgang Denk | 74f9b38 | 2011-07-30 13:33:49 +0000 | [diff] [blame] | 293 | const void *fit_data; |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 294 | |
| 295 | if (fit_uname == NULL) { |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 296 | puts("No FIT subimage unit name\n"); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 297 | return 1; |
| 298 | } |
| 299 | |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 300 | if (!fit_check_format(fit_hdr)) { |
| 301 | puts("Bad FIT image format\n"); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 302 | return 1; |
| 303 | } |
| 304 | |
| 305 | /* get fpga component image node offset */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 306 | noffset = fit_image_get_node(fit_hdr, |
| 307 | fit_uname); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 308 | if (noffset < 0) { |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 309 | printf("Can't find '%s' FIT subimage\n", |
| 310 | fit_uname); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 311 | return 1; |
| 312 | } |
| 313 | |
| 314 | /* verify integrity */ |
Simon Glass | 7428ad1 | 2013-05-07 06:11:57 +0000 | [diff] [blame] | 315 | if (!fit_image_verify(fit_hdr, noffset)) { |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 316 | puts ("Bad Data Hash\n"); |
| 317 | return 1; |
| 318 | } |
| 319 | |
| 320 | /* get fpga subimage data address and length */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 321 | if (fit_image_get_data(fit_hdr, noffset, |
| 322 | &fit_data, &data_size)) { |
| 323 | puts("Fpga subimage data not found\n"); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 324 | return 1; |
| 325 | } |
| 326 | |
Michal Simek | 1466365 | 2014-05-02 14:09:30 +0200 | [diff] [blame] | 327 | rc = fpga_load(dev, fit_data, data_size, |
| 328 | BIT_FULL); |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 329 | } |
Marian Balakowicz | dbdd16a | 2008-02-04 08:28:09 +0100 | [diff] [blame] | 330 | break; |
| 331 | #endif |
| 332 | default: |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 333 | puts("** Unknown image type\n"); |
Marian Balakowicz | dbdd16a | 2008-02-04 08:28:09 +0100 | [diff] [blame] | 334 | rc = FPGA_FAIL; |
| 335 | break; |
Stefan Roese | 5f1cf2d | 2006-08-15 14:15:51 +0200 | [diff] [blame] | 336 | } |
| 337 | break; |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 338 | #endif |
Stefan Roese | 5f1cf2d | 2006-08-15 14:15:51 +0200 | [diff] [blame] | 339 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 340 | case FPGA_DUMP: |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 341 | rc = fpga_dump(dev, fpga_data, data_size); |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 342 | break; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 343 | |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 344 | default: |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 345 | printf("Unknown operation\n"); |
Simon Glass | a06dfc7 | 2011-12-10 08:44:01 +0000 | [diff] [blame] | 346 | return CMD_RET_USAGE; |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 347 | } |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 348 | return rc; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 349 | } |
| 350 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 351 | /* |
| 352 | * Map op to supported operations. We don't use a table since we |
| 353 | * would just have to relocate it from flash anyway. |
| 354 | */ |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 355 | static int fpga_get_op(char *opstr) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 356 | { |
| 357 | int op = FPGA_NONE; |
| 358 | |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 359 | if (!strcmp("info", opstr)) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 360 | op = FPGA_INFO; |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 361 | else if (!strcmp("loadb", opstr)) |
wdenk | 310b4fc | 2005-01-09 18:12:51 +0000 | [diff] [blame] | 362 | op = FPGA_LOADB; |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 363 | else if (!strcmp("load", opstr)) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 364 | op = FPGA_LOAD; |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 365 | #if defined(CONFIG_CMD_FPGA_LOADP) |
| 366 | else if (!strcmp("loadp", opstr)) |
| 367 | op = FPGA_LOADP; |
| 368 | #endif |
| 369 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
| 370 | else if (!strcmp("loadbp", opstr)) |
| 371 | op = FPGA_LOADBP; |
| 372 | #endif |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 373 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
| 374 | else if (!strcmp("loadfs", opstr)) |
| 375 | op = FPGA_LOADFS; |
| 376 | #endif |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 377 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 378 | else if (!strcmp("loadmk", opstr)) |
Stefan Roese | 5f1cf2d | 2006-08-15 14:15:51 +0200 | [diff] [blame] | 379 | op = FPGA_LOADMK; |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 380 | #endif |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 381 | else if (!strcmp("dump", opstr)) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 382 | op = FPGA_DUMP; |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 383 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 384 | else if (!strcmp("loads", opstr)) |
| 385 | op = FPGA_LOADS; |
| 386 | #endif |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 387 | |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 388 | if (op == FPGA_NONE) |
| 389 | printf("Unknown fpga operation \"%s\"\n", opstr); |
| 390 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 391 | return op; |
| 392 | } |
| 393 | |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 394 | #if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 395 | U_BOOT_CMD(fpga, 9, 1, do_fpga, |
| 396 | #else |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 397 | U_BOOT_CMD(fpga, 6, 1, do_fpga, |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 398 | #endif |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 399 | "loadable FPGA image support", |
| 400 | "[operation type] [device number] [image address] [image size]\n" |
| 401 | "fpga operations:\n" |
Michal Simek | 70da592 | 2015-01-26 08:52:27 +0100 | [diff] [blame] | 402 | " dump\t[dev] [address] [size]\tLoad device to memory buffer\n" |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 403 | " info\t[dev]\t\t\tlist known device information\n" |
| 404 | " load\t[dev] [address] [size]\tLoad device from memory buffer\n" |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 405 | #if defined(CONFIG_CMD_FPGA_LOADP) |
| 406 | " loadp\t[dev] [address] [size]\t" |
| 407 | "Load device from memory buffer with partial bitstream\n" |
| 408 | #endif |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 409 | " loadb\t[dev] [address] [size]\t" |
| 410 | "Load device from bitstream buffer (Xilinx only)\n" |
Michal Simek | 64c7098 | 2014-05-02 13:43:39 +0200 | [diff] [blame] | 411 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
| 412 | " loadbp\t[dev] [address] [size]\t" |
| 413 | "Load device from bitstream buffer with partial bitstream" |
| 414 | "(Xilinx only)\n" |
| 415 | #endif |
Siva Durga Prasad Paladugu | 9112b4c | 2014-03-14 16:35:37 +0530 | [diff] [blame] | 416 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
| 417 | "Load device from filesystem (FAT by default) (Xilinx only)\n" |
| 418 | " loadfs [dev] [address] [image size] [blocksize] <interface>\n" |
| 419 | " [<dev[:part]>] <filename>\n" |
| 420 | #endif |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 421 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 422 | " loadmk [dev] [address]\tLoad device generated with mkimage" |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 423 | #if defined(CONFIG_FIT) |
Michal Simek | a888af7 | 2013-04-26 13:10:07 +0200 | [diff] [blame] | 424 | "\n" |
| 425 | "\tFor loadmk operating on FIT format uImage address must include\n" |
| 426 | "\tsubimage unit name in the form of addr:<subimg_uname>" |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 427 | #endif |
Siva Durga Prasad Paladugu | adc11de | 2014-03-14 16:35:38 +0530 | [diff] [blame] | 428 | #endif |
Siva Durga Prasad Paladugu | cce0cb0 | 2018-05-31 15:10:22 +0530 | [diff] [blame] | 429 | #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) |
| 430 | "Load encrypted bitstream (Xilinx only)\n" |
| 431 | " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n" |
| 432 | " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n" |
| 433 | "Loads the secure bistreams(authenticated/encrypted/both\n" |
| 434 | "authenticated and encrypted) of [size] from [address].\n" |
| 435 | "The auth-OCM/DDR flag specifies to perform authentication\n" |
| 436 | "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n" |
| 437 | "The enc flag specifies which key to be used for decryption\n" |
| 438 | "0-device key, 1-user key, 2-no encryption.\n" |
| 439 | "The optional Userkey address specifies from which address key\n" |
| 440 | "has to be used for decryption if user key is selected.\n" |
| 441 | "NOTE: the sceure bitstream has to be created using xilinx\n" |
| 442 | "bootgen tool only.\n" |
| 443 | #endif |
Marian Balakowicz | d79162d | 2008-03-12 10:33:01 +0100 | [diff] [blame] | 444 | ); |