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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hud2396512016-09-07 18:47:28 +08002/*
3 * Copyright 2016 Freescale Semiconductor
Mingkai Hud2396512016-09-07 18:47:28 +08004 */
5
6#ifndef __LS1046A_COMMON_H
7#define __LS1046A_COMMON_H
8
Sumit Gargc064fc72017-03-30 09:53:13 +05309/* SPL build */
10#ifdef CONFIG_SPL_BUILD
11#define SPL_NO_QBMAN
12#define SPL_NO_FMAN
13#define SPL_NO_ENV
14#define SPL_NO_MISC
15#define SPL_NO_QSPI
16#define SPL_NO_USB
17#define SPL_NO_SATA
18#endif
19#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
20#define SPL_NO_MMC
21#endif
22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
23#define SPL_NO_IFC
24#endif
25
Mingkai Hud2396512016-09-07 18:47:28 +080026#define CONFIG_REMAKE_ELF
27#define CONFIG_FSL_LAYERSCAPE
Mingkai Hud2396512016-09-07 18:47:28 +080028#define CONFIG_MP
Mingkai Hud2396512016-09-07 18:47:28 +080029#define CONFIG_GICV2
30
31#include <asm/arch/config.h>
Bharat Bhushanc882dd72017-03-22 12:06:28 +053032#include <asm/arch/stream_id_lsch2.h>
Mingkai Hud2396512016-09-07 18:47:28 +080033
34/* Link Definitions */
35#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
36
Mingkai Hud2396512016-09-07 18:47:28 +080037#define CONFIG_SKIP_LOWLEVEL_INIT
Mingkai Hud2396512016-09-07 18:47:28 +080038
39#define CONFIG_VERY_BIG_RAM
40#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
41#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
42#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
43#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
44
45#define CPU_RELEASE_ADDR secondary_boot_func
46
47/* Generic Timer Definitions */
48#define COUNTER_FREQUENCY 25000000 /* 25MHz */
49
50/* Size of malloc() pool */
51#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
52
53/* Serial Port */
Mingkai Hud2396512016-09-07 18:47:28 +080054#define CONFIG_SYS_NS16550_SERIAL
55#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +080056#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Hud2396512016-09-07 18:47:28 +080057
Mingkai Hud2396512016-09-07 18:47:28 +080058#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
59
60/* SD boot SPL */
61#ifdef CONFIG_SD_BOOT
Mingkai Hud2396512016-09-07 18:47:28 +080062#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
63#define CONFIG_SPL_LIBCOMMON_SUPPORT
64#define CONFIG_SPL_LIBGENERIC_SUPPORT
65#define CONFIG_SPL_ENV_SUPPORT
66#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
67#define CONFIG_SPL_WATCHDOG_SUPPORT
68#define CONFIG_SPL_I2C_SUPPORT
Mingkai Hud2396512016-09-07 18:47:28 +080069#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
70
71#define CONFIG_SPL_MMC_SUPPORT
Mingkai Hud2396512016-09-07 18:47:28 +080072#define CONFIG_SPL_TEXT_BASE 0x10000000
73#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
74#define CONFIG_SPL_STACK 0x10020000
75#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
76#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
77#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
78#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
79 CONFIG_SPL_BSS_MAX_SIZE)
80#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
Ruchika Gupta0009c8f2017-04-17 18:07:19 +053081
82#ifdef CONFIG_SECURE_BOOT
83#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
84/*
85 * HDR would be appended at end of image and copied to DDR along
86 * with U-Boot image. Here u-boot max. size is 512K. So if binary
87 * size increases then increase this size in case of secure boot as
88 * it uses raw u-boot image instead of fit image.
89 */
90#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
91#else
92#define CONFIG_SYS_MONITOR_LEN 0x100000
93#endif /* ifdef CONFIG_SECURE_BOOT */
Mingkai Hud2396512016-09-07 18:47:28 +080094#endif
95
Shaohui Xie085ac1c2016-09-07 17:56:14 +080096/* NAND SPL */
97#ifdef CONFIG_NAND_BOOT
98#define CONFIG_SPL_PBL_PAD
Shaohui Xie085ac1c2016-09-07 17:56:14 +080099#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
100#define CONFIG_SPL_LIBCOMMON_SUPPORT
101#define CONFIG_SPL_LIBGENERIC_SUPPORT
102#define CONFIG_SPL_ENV_SUPPORT
103#define CONFIG_SPL_WATCHDOG_SUPPORT
104#define CONFIG_SPL_I2C_SUPPORT
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800105#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
106
107#define CONFIG_SPL_NAND_SUPPORT
108#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
109#define CONFIG_SPL_TEXT_BASE 0x10000000
Ruchika Gupta0009c8f2017-04-17 18:07:19 +0530110#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800111#define CONFIG_SPL_STACK 0x1001f000
112#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
113#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
114
115#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
116#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
117#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
118 CONFIG_SPL_BSS_MAX_SIZE)
119#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
120#define CONFIG_SYS_MONITOR_LEN 0xa0000
121#endif
122
Mingkai Hud2396512016-09-07 18:47:28 +0800123/* I2C */
124#define CONFIG_SYS_I2C
Mingkai Hud2396512016-09-07 18:47:28 +0800125
Hou Zhiqiang105457e2017-04-14 16:49:01 +0800126/* PCIe */
127#define CONFIG_PCIE1 /* PCIE controller 1 */
128#define CONFIG_PCIE2 /* PCIE controller 2 */
129#define CONFIG_PCIE3 /* PCIE controller 3 */
130
131#ifdef CONFIG_PCI
132#define CONFIG_PCI_SCAN_SHOW
Hou Zhiqiang105457e2017-04-14 16:49:01 +0800133#endif
134
Yuantian Tangd24716d2018-01-03 15:53:09 +0800135/* SATA */
136#ifndef SPL_NO_SATA
137#define CONFIG_SCSI_AHCI_PLAT
138
139#define CONFIG_SYS_SATA AHCI_BASE_ADDR
140
141#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
142#define CONFIG_SYS_SCSI_MAX_LUN 1
143#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
144 CONFIG_SYS_SCSI_MAX_LUN)
145#endif
146
Mingkai Hud2396512016-09-07 18:47:28 +0800147/* Command line configuration */
Mingkai Hud2396512016-09-07 18:47:28 +0800148
149/* MMC */
Sumit Gargc064fc72017-03-30 09:53:13 +0530150#ifndef SPL_NO_MMC
Mingkai Hud2396512016-09-07 18:47:28 +0800151#ifdef CONFIG_MMC
Mingkai Hud2396512016-09-07 18:47:28 +0800152#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Mingkai Hud2396512016-09-07 18:47:28 +0800153#endif
Sumit Gargc064fc72017-03-30 09:53:13 +0530154#endif
Mingkai Hud2396512016-09-07 18:47:28 +0800155
Mingkai Hud2396512016-09-07 18:47:28 +0800156/* FMan ucode */
Sumit Gargc064fc72017-03-30 09:53:13 +0530157#ifndef SPL_NO_FMAN
Mingkai Hud2396512016-09-07 18:47:28 +0800158#define CONFIG_SYS_DPAA_FMAN
159#ifdef CONFIG_SYS_DPAA_FMAN
160#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
Sumit Gargc064fc72017-03-30 09:53:13 +0530161#endif
Mingkai Hud2396512016-09-07 18:47:28 +0800162
163#ifdef CONFIG_SD_BOOT
164/*
165 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
166 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
Alison Wang42f37802017-05-16 10:45:59 +0800167 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
Mingkai Hud2396512016-09-07 18:47:28 +0800168 */
169#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Alison Wang42f37802017-05-16 10:45:59 +0800170#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800171#elif defined(CONFIG_QSPI_BOOT)
Mingkai Hud2396512016-09-07 18:47:28 +0800172#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Alison Wang42f37802017-05-16 10:45:59 +0800173#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
Mingkai Hud2396512016-09-07 18:47:28 +0800174#define CONFIG_ENV_SPI_BUS 0
175#define CONFIG_ENV_SPI_CS 0
176#define CONFIG_ENV_SPI_MAX_HZ 1000000
177#define CONFIG_ENV_SPI_MODE 0x03
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800178#elif defined(CONFIG_NAND_BOOT)
179#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Gong Qianyub91b5cf2017-09-18 16:59:28 +0800180#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800181#else
182#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Alison Wang42f37802017-05-16 10:45:59 +0800183#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
Mingkai Hud2396512016-09-07 18:47:28 +0800184#endif
185#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
186#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
187#endif
188
189/* Miscellaneous configurable options */
190#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
Mingkai Hud2396512016-09-07 18:47:28 +0800191
192#define CONFIG_HWCONFIG
193#define HWCONFIG_BUFFER_SIZE 128
194
Qianyu Gong6264ab62017-06-15 11:10:09 +0800195#ifndef CONFIG_SPL_BUILD
196#define BOOT_TARGET_DEVICES(func) \
Yuantian Tangd24716d2018-01-03 15:53:09 +0800197 func(SCSI, scsi, 0) \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800198 func(MMC, mmc, 0) \
199 func(USB, usb, 0)
200#include <config_distro_bootcmd.h>
201#endif
202
Sumit Gargc064fc72017-03-30 09:53:13 +0530203#ifndef SPL_NO_MISC
Mingkai Hud2396512016-09-07 18:47:28 +0800204/* Initial environment variables */
205#define CONFIG_EXTRA_ENV_SETTINGS \
206 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800207 "ramdisk_addr=0x800000\0" \
208 "ramdisk_size=0x2000000\0" \
209 "fdt_high=0xffffffffffffffff\0" \
210 "initrd_high=0xffffffffffffffff\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800211 "fdt_addr=0x64f00000\0" \
212 "kernel_addr=0x65000000\0" \
213 "scriptaddr=0x80000000\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530214 "scripthdraddr=0x80080000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800215 "fdtheader_addr_r=0x80100000\0" \
216 "kernelheader_addr_r=0x80200000\0" \
217 "load_addr=0xa0000000\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530218 "kernel_addr_r=0x81000000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800219 "fdt_addr_r=0x90000000\0" \
220 "ramdisk_addr_r=0xa0000000\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800221 "kernel_start=0x1000000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530222 "kernelheader_start=0x800000\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800223 "kernel_load=0xa0000000\0" \
224 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530225 "kernelheader_size=0x40000\0" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800226 "kernel_addr_sd=0x8000\0" \
227 "kernel_size_sd=0x14000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530228 "kernelhdr_addr_sd=0x4000\0" \
229 "kernelhdr_size_sd=0x10\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800230 "console=ttyS0,115200\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400231 CONFIG_MTDPARTS_DEFAULT "\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800232 BOOTENV \
233 "boot_scripts=ls1046ardb_boot.scr\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530234 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800235 "scan_dev_for_boot_part=" \
236 "part list ${devtype} ${devnum} devplist; " \
237 "env exists devplist || setenv devplist 1; " \
238 "for distro_bootpart in ${devplist}; do " \
239 "if fstype ${devtype} " \
240 "${devnum}:${distro_bootpart} " \
241 "bootfstype; then " \
242 "run scan_dev_for_boot; " \
243 "fi; " \
244 "done\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530245 "scan_dev_for_boot=" \
246 "echo Scanning ${devtype} " \
247 "${devnum}:${distro_bootpart}...; " \
248 "for prefix in ${boot_prefixes}; do " \
249 "run scan_dev_for_scripts; " \
250 "done;" \
251 "\0" \
252 "boot_a_script=" \
253 "load ${devtype} ${devnum}:${distro_bootpart} " \
254 "${scriptaddr} ${prefix}${script}; " \
255 "env exists secureboot && load ${devtype} " \
256 "${devnum}:${distro_bootpart} " \
257 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
258 "&& esbc_validate ${scripthdraddr};" \
259 "source ${scriptaddr}\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800260 "qspi_bootcmd=echo Trying load from qspi..;" \
261 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530262 "$kernel_start $kernel_size; env exists secureboot " \
263 "&& sf read $kernelheader_addr_r $kernelheader_start " \
264 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
265 "bootm $load_addr#$board\0" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800266 "sd_bootcmd=echo Trying load from SD ..;" \
267 "mmcinfo; mmc read $load_addr " \
268 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530269 "env exists secureboot && mmc read $kernelheader_addr_r " \
270 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
271 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800272 "bootm $load_addr#$board\0"
Qianyu Gong6264ab62017-06-15 11:10:09 +0800273
Sumit Gargc064fc72017-03-30 09:53:13 +0530274#endif
275
Mingkai Hud2396512016-09-07 18:47:28 +0800276/* Monitor Command Prompt */
277#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sumit Gargc064fc72017-03-30 09:53:13 +0530278
Mingkai Hud2396512016-09-07 18:47:28 +0800279#define CONFIG_SYS_MAXARGS 64 /* max command args */
280
281#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
282
Simon Glass89e0a3a2017-05-17 08:23:10 -0600283#include <asm/arch/soc.h>
284
Mingkai Hud2396512016-09-07 18:47:28 +0800285#endif /* __LS1046A_COMMON_H */