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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +09002/*
3 * include/configs/gose.h
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +09006 */
7
8#ifndef __GOSE_H
9#define __GOSE_H
10
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090011#include "rcar-gen2-common.h"
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090012
Marek Vasut2d6dabc2018-04-23 20:24:10 +020013#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
14#define STACK_AREA_SIZE 0x00100000
15#define LOW_LEVEL_MERAM_STACK \
16 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090017
18/* MEMORY */
Nobuhiro Iwamatsub6169ac2014-11-10 14:34:07 +090019#define RCAR_GEN2_SDRAM_BASE 0x40000000
Marek Vasut2d6dabc2018-04-23 20:24:10 +020020#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
21#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090022
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090023/* SH Ether */
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090024#define CONFIG_SH_ETHER_USE_PORT 0
25#define CONFIG_SH_ETHER_PHY_ADDR 0x1
26#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
27#define CONFIG_SH_ETHER_CACHE_WRITEBACK
28#define CONFIG_SH_ETHER_CACHE_INVALIDATE
Marek Vasut2d6dabc2018-04-23 20:24:10 +020029#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090030#define CONFIG_BITBANGMII
31#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsueef1f232014-11-06 15:42:24 +090032
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090033/* Board Clock */
34#define RMOBILE_XTAL_CLK 20000000u
35#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
36#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090037
Marek Vasut2d6dabc2018-04-23 20:24:10 +020038#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu87adc0a2014-11-06 15:42:25 +090039
Marek Vasut2d6dabc2018-04-23 20:24:10 +020040#define CONFIG_EXTRA_ENV_SETTINGS \
41 "fdt_high=0xffffffff\0" \
42 "initrd_high=0xffffffff\0"
Nobuhiro Iwamatsue02f1742014-12-02 16:52:24 +090043
Marek Vasut2d6dabc2018-04-23 20:24:10 +020044/* SPL support */
45#define CONFIG_SPL_TEXT_BASE 0xe6300000
46#define CONFIG_SPL_STACK 0xe6340000
47#define CONFIG_SPL_MAX_SIZE 0x4000
48#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_CONS_SCIF0
51#define CONFIG_SH_SCIF_CLK_FREQ 65000000
52#endif
Nobuhiro Iwamatsu161af502014-11-12 11:29:39 +090053
Nobuhiro Iwamatsu7e405632014-11-06 15:39:28 +090054#endif /* __GOSE_H */