| Greg Malysa | eabf232 | 2025-02-26 12:30:29 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /** |
| 3 | * (C) Copyright 2024 - Analog Devices, Inc. |
| 4 | * |
| 5 | * Written and/or maintained by Timesys Corporation |
| 6 | * |
| 7 | * Author: Greg Malysa <greg.malysa@timesys.com> |
| 8 | * Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> |
| 9 | */ |
| 10 | |
| 11 | #include <clk.h> |
| 12 | #include <dm.h> |
| 13 | #include <net.h> |
| 14 | #include <phy.h> |
| 15 | #include <reset.h> |
| 16 | #include <linux/io.h> |
| 17 | |
| 18 | #include <asm/arch-adi/sc5xx/sc5xx.h> |
| 19 | |
| 20 | #include "dwc_eth_qos.h" |
| 21 | |
| 22 | static int eqos_start_resets_adi(struct udevice *dev) |
| 23 | { |
| 24 | struct eqos_priv *eqos = dev_get_priv(dev); |
| 25 | |
| 26 | /* |
| 27 | * Settings need to latch with the DMA reset below. Currently only |
| 28 | * rgmii is supported but other phy interfaces may be supported in |
| 29 | * the future |
| 30 | */ |
| 31 | sc5xx_enable_rgmii(); |
| 32 | setbits_32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR); |
| 33 | |
| 34 | return 0; |
| 35 | } |
| 36 | |
| 37 | static int eqos_probe_resources_adi(struct udevice *dev) |
| 38 | { |
| 39 | struct eqos_priv *eqos = dev_get_priv(dev); |
| 40 | phy_interface_t interface; |
| 41 | int ret; |
| 42 | |
| 43 | ret = eqos_get_base_addr_dt(dev); |
| 44 | if (ret) { |
| 45 | pr_err("eqos_get_base_addr_dt failed: %d\n", ret); |
| 46 | return ret; |
| 47 | } |
| 48 | |
| 49 | interface = eqos->config->interface(dev); |
| 50 | if (interface == PHY_INTERFACE_MODE_NA) { |
| 51 | pr_err("Invalid PHY interface\n"); |
| 52 | return -EINVAL; |
| 53 | } |
| 54 | |
| 55 | return 0; |
| 56 | } |
| 57 | |
| 58 | /** |
| 59 | * rgmii tx clock rate is set to 125 MHz regardless of phy mode, and |
| 60 | * by default the internal clock is always connected to 125 MHz. According |
| 61 | * to the HRM it is invalid for this clock to have any other speed, so |
| 62 | * the hardware won't work anyway if this is wrong. |
| 63 | */ |
| 64 | static ulong eqos_get_tick_clk_rate_adi(struct udevice *dev) |
| 65 | { |
| 66 | return 125 * 1000000; |
| 67 | } |
| 68 | |
| 69 | static int eqos_get_enetaddr_adi(struct udevice *dev) |
| 70 | { |
| 71 | struct eth_pdata *pdata = dev_get_plat(dev); |
| 72 | |
| 73 | return eth_env_get_enetaddr("ethaddr", pdata->enetaddr); |
| 74 | } |
| 75 | |
| 76 | static struct eqos_ops eqos_adi_ops = { |
| 77 | .eqos_inval_desc = eqos_inval_desc_generic, |
| 78 | .eqos_flush_desc = eqos_flush_desc_generic, |
| 79 | .eqos_inval_buffer = eqos_inval_buffer_generic, |
| 80 | .eqos_flush_buffer = eqos_flush_buffer_generic, |
| 81 | .eqos_probe_resources = eqos_probe_resources_adi, |
| 82 | .eqos_remove_resources = eqos_null_ops, |
| 83 | .eqos_start_resets = eqos_start_resets_adi, |
| 84 | .eqos_stop_resets = eqos_null_ops, |
| 85 | .eqos_start_clks = eqos_null_ops, |
| 86 | .eqos_stop_clks = eqos_null_ops, |
| 87 | .eqos_calibrate_pads = eqos_null_ops, |
| 88 | .eqos_disable_calibration = eqos_null_ops, |
| 89 | .eqos_set_tx_clk_speed = eqos_null_ops, |
| 90 | .eqos_get_enetaddr = eqos_get_enetaddr_adi, |
| 91 | .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_adi, |
| 92 | }; |
| 93 | |
| 94 | struct eqos_config __maybe_unused eqos_adi_config = { |
| 95 | .reg_access_always_ok = true, |
| 96 | .mdio_wait = 20, |
| 97 | .swr_wait = 50, |
| 98 | .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, |
| 99 | .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_150_250, |
| 100 | .axi_bus_width = EQOS_AXI_WIDTH_32, |
| 101 | .interface = dev_read_phy_mode, |
| 102 | .ops = &eqos_adi_ops, |
| 103 | }; |