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Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver
4 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -05005 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05306 */
7
Vignesh Raghavendra197e5c22019-12-09 10:25:33 +05308#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060010#include <asm/cache.h>
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053011#include <asm/io.h>
12#include <malloc.h>
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053013#include <asm/bitops.h>
14#include <dm.h>
Simon Glass9bc15642020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070016#include <dm/devres.h>
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053017#include <dm/read.h>
18#include <dm/uclass.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060019#include <linux/bitops.h>
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053020#include <linux/compat.h>
Masahiro Yamada6373a172020-02-14 16:40:19 +090021#include <linux/dma-mapping.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070022#include <linux/err.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060023#include <linux/printk.h>
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053024#include <linux/soc/ti/k3-navss-ringacc.h>
25#include <linux/soc/ti/ti_sci_protocol.h>
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +053026#include <linux/soc/ti/cppi5.h>
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053027
28#define set_bit(bit, bitmap) __set_bit(bit, bitmap)
29#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap)
30#define dma_free_coherent(dev, size, cpu_addr, dma_handle) \
31 dma_free_coherent(cpu_addr)
32#define dma_zalloc_coherent(dev, size, dma_handle, flag) \
33({ \
34 void *ring_mem_virt; \
35 ring_mem_virt = dma_alloc_coherent((size), \
36 (unsigned long *)(dma_handle)); \
37 if (ring_mem_virt) \
38 memset(ring_mem_virt, 0, (size)); \
39 ring_mem_virt; \
40})
41
42static LIST_HEAD(k3_nav_ringacc_list);
43
44static void ringacc_writel(u32 v, void __iomem *reg)
45{
46 pr_debug("WRITEL(32): v(%08X)-->reg(%p)\n", v, reg);
47 writel(v, reg);
48}
49
50static u32 ringacc_readl(void __iomem *reg)
51{
52 u32 v;
53
54 v = readl(reg);
55 pr_debug("READL(32): v(%08X)<--reg(%p)\n", v, reg);
56 return v;
57}
58
59#define KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK GENMASK(19, 0)
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +053060#define K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK GENMASK(15, 0)
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053061
62/**
63 * struct k3_nav_ring_rt_regs - The RA Control/Status Registers region
64 */
65struct k3_nav_ring_rt_regs {
66 u32 resv_16[4];
67 u32 db; /* RT Ring N Doorbell Register */
68 u32 resv_4[1];
69 u32 occ; /* RT Ring N Occupancy Register */
70 u32 indx; /* RT Ring N Current Index Register */
71 u32 hwocc; /* RT Ring N Hardware Occupancy Register */
72 u32 hwindx; /* RT Ring N Current Index Register */
73};
74
75#define KNAV_RINGACC_RT_REGS_STEP 0x1000
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +053076#define K3_DMARING_RING_RT_REGS_STEP 0x2000
77#define K3_DMARING_RING_RT_REGS_REVERSE_OFS 0x1000
78#define KNAV_RINGACC_RT_OCC_MASK GENMASK(20, 0)
79#define K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE BIT(31)
80#define K3_DMARING_RING_RT_DB_ENTRY_MASK GENMASK(7, 0)
81#define K3_DMARING_RING_RT_DB_TDOWN_ACK BIT(31)
82
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053083/**
84 * struct k3_nav_ring_fifo_regs - The Ring Accelerator Queues Registers region
85 */
86struct k3_nav_ring_fifo_regs {
87 u32 head_data[128]; /* Ring Head Entry Data Registers */
88 u32 tail_data[128]; /* Ring Tail Entry Data Registers */
89 u32 peek_head_data[128]; /* Ring Peek Head Entry Data Regs */
90 u32 peek_tail_data[128]; /* Ring Peek Tail Entry Data Regs */
91};
92
Grygorii Strashko1c5258f2019-02-05 17:31:22 +053093#define KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES (512U)
94#define KNAV_RINGACC_FIFO_REGS_STEP 0x1000
95#define KNAV_RINGACC_MAX_DB_RING_CNT (127U)
96
97/**
98 * struct k3_nav_ring_ops - Ring operations
99 */
100struct k3_nav_ring_ops {
101 int (*push_tail)(struct k3_nav_ring *ring, void *elm);
102 int (*push_head)(struct k3_nav_ring *ring, void *elm);
103 int (*pop_tail)(struct k3_nav_ring *ring, void *elm);
104 int (*pop_head)(struct k3_nav_ring *ring, void *elm);
105};
106
107/**
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530108 * struct k3_nav_ring_state - Internal state tracking structure
109 *
110 * @free: Number of free entries
111 * @occ: Occupancy
112 * @windex: Write index
113 * @rindex: Read index
114 */
115struct k3_nav_ring_state {
116 u32 free;
117 u32 occ;
118 u32 windex;
119 u32 rindex;
120 u32 tdown_complete:1;
121};
122
123/**
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530124 * struct k3_nav_ring - RA Ring descriptor
125 *
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530126 * @cfg - Ring configuration registers
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530127 * @rt - Ring control/status registers
128 * @fifos - Ring queues registers
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530129 * @ring_mem_dma - Ring buffer dma address
130 * @ring_mem_virt - Ring buffer virt address
131 * @ops - Ring operations
132 * @size - Ring size in elements
133 * @elm_size - Size of the ring element
134 * @mode - Ring mode
135 * @flags - flags
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530136 * @ring_id - Ring Id
137 * @parent - Pointer on struct @k3_nav_ringacc
138 * @use_count - Use count for shared rings
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530139 */
140struct k3_nav_ring {
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530141 struct k3_nav_ring_cfg_regs __iomem *cfg;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530142 struct k3_nav_ring_rt_regs __iomem *rt;
143 struct k3_nav_ring_fifo_regs __iomem *fifos;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530144 dma_addr_t ring_mem_dma;
145 void *ring_mem_virt;
146 struct k3_nav_ring_ops *ops;
147 u32 size;
148 enum k3_nav_ring_size elm_size;
149 enum k3_nav_ring_mode mode;
150 u32 flags;
151#define KNAV_RING_FLAG_BUSY BIT(1)
152#define K3_NAV_RING_FLAG_SHARED BIT(2)
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530153#define K3_NAV_RING_FLAG_REVERSE BIT(3)
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530154 struct k3_nav_ring_state state;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530155 u32 ring_id;
156 struct k3_nav_ringacc *parent;
157 u32 use_count;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530158};
159
Vignesh Raghavendrab627aad2020-07-06 13:26:24 +0530160struct k3_nav_ringacc_ops {
161 int (*init)(struct udevice *dev, struct k3_nav_ringacc *ringacc);
162};
163
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530164/**
165 * struct k3_nav_ringacc - Rings accelerator descriptor
166 *
167 * @dev - pointer on RA device
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530168 * @num_rings - number of ring in RA
169 * @rm_gp_range - general purpose rings range from tisci
170 * @dma_ring_reset_quirk - DMA reset w/a enable
171 * @num_proxies - number of RA proxies
172 * @rings - array of rings descriptors (struct @k3_nav_ring)
173 * @list - list of RAs in the system
174 * @tisci - pointer ti-sci handle
175 * @tisci_ring_ops - ti-sci rings ops
176 * @tisci_dev_id - ti-sci device id
Vignesh Raghavendrab627aad2020-07-06 13:26:24 +0530177 * @ops: SoC specific ringacc operation
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530178 * @dual_ring: indicate k3_dmaring dual ring support
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530179 */
180struct k3_nav_ringacc {
181 struct udevice *dev;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530182 u32 num_rings; /* number of rings in Ringacc module */
183 unsigned long *rings_inuse;
184 struct ti_sci_resource *rm_gp_range;
185 bool dma_ring_reset_quirk;
186 u32 num_proxies;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530187
188 struct k3_nav_ring *rings;
189 struct list_head list;
190
191 const struct ti_sci_handle *tisci;
192 const struct ti_sci_rm_ringacc_ops *tisci_ring_ops;
193 u32 tisci_dev_id;
Vignesh Raghavendrab627aad2020-07-06 13:26:24 +0530194
195 const struct k3_nav_ringacc_ops *ops;
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530196 bool dual_ring;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530197};
198
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530199#include "k3-navss-ringacc-u-boot.c"
200
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530201static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
202{
203 return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
204}
205
206static void k3_nav_ringacc_ring_update_occ(struct k3_nav_ring *ring)
207{
208 u32 val;
209
210 val = readl(&ring->rt->occ);
211
212 ring->state.occ = val & KNAV_RINGACC_RT_OCC_MASK;
213 ring->state.tdown_complete = !!(val & K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE);
214}
215
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530216static void *k3_nav_ringacc_get_elm_addr(struct k3_nav_ring *ring, u32 idx)
217{
218 return (idx * (4 << ring->elm_size) + ring->ring_mem_virt);
219}
220
221static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem);
222static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem);
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530223static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem);
224static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530225
226static struct k3_nav_ring_ops k3_nav_mode_ring_ops = {
227 .push_tail = k3_nav_ringacc_ring_push_mem,
228 .pop_head = k3_nav_ringacc_ring_pop_mem,
229};
230
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530231static struct k3_nav_ring_ops k3_dmaring_fwd_ring_ops = {
232 .push_tail = k3_nav_ringacc_ring_push_mem,
233 .pop_head = k3_dmaring_ring_fwd_pop_mem,
234};
235
236static struct k3_nav_ring_ops k3_dmaring_reverse_ring_ops = {
237 .pop_head = k3_dmaring_ring_reverse_pop_mem,
238};
239
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530240struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc)
241{
242 return ringacc->dev;
243}
244
245struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
Vignesh Raghavendra923eeaf2021-05-10 20:06:04 +0530246 int id)
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530247{
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530248 if (id == K3_NAV_RINGACC_RING_ID_ANY) {
249 /* Request for any general purpose ring */
250 struct ti_sci_resource_desc *gp_rings =
251 &ringacc->rm_gp_range->desc[0];
252 unsigned long size;
253
254 size = gp_rings->start + gp_rings->num;
255 id = find_next_zero_bit(ringacc->rings_inuse,
256 size, gp_rings->start);
257 if (id == size)
258 goto error;
259 } else if (id < 0) {
260 goto error;
261 }
262
263 if (test_bit(id, ringacc->rings_inuse) &&
264 !(ringacc->rings[id].flags & K3_NAV_RING_FLAG_SHARED))
265 goto error;
266 else if (ringacc->rings[id].flags & K3_NAV_RING_FLAG_SHARED)
267 goto out;
268
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530269 if (!try_module_get(ringacc->dev->driver->owner))
270 goto error;
271
Vignesh Raghavendra923eeaf2021-05-10 20:06:04 +0530272 pr_debug("Giving ring#%d\n", id);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530273
274 set_bit(id, ringacc->rings_inuse);
275out:
276 ringacc->rings[id].use_count++;
277 return &ringacc->rings[id];
278
279error:
280 return NULL;
281}
282
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530283static int k3_dmaring_ring_request_rings_pair(struct k3_nav_ringacc *ringacc,
284 int fwd_id, int compl_id,
285 struct k3_nav_ring **fwd_ring,
286 struct k3_nav_ring **compl_ring)
287{
288 /* k3_dmaring: fwd_id == compl_id, so we ignore compl_id */
289 if (fwd_id < 0)
290 return -EINVAL;
291
292 if (test_bit(fwd_id, ringacc->rings_inuse))
293 return -EBUSY;
294
295 *fwd_ring = &ringacc->rings[fwd_id];
296 *compl_ring = &ringacc->rings[fwd_id + ringacc->num_rings];
297 set_bit(fwd_id, ringacc->rings_inuse);
298 ringacc->rings[fwd_id].use_count++;
299 dev_dbg(ringacc->dev, "Giving ring#%d\n", fwd_id);
300
301 return 0;
302}
303
Vignesh Raghavendra9a7ad5e2020-07-06 13:26:23 +0530304int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
305 int fwd_id, int compl_id,
306 struct k3_nav_ring **fwd_ring,
307 struct k3_nav_ring **compl_ring)
308{
309 int ret = 0;
310
311 if (!fwd_ring || !compl_ring)
312 return -EINVAL;
313
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530314 if (ringacc->dual_ring)
315 return k3_dmaring_ring_request_rings_pair(ringacc, fwd_id, compl_id,
316 fwd_ring, compl_ring);
317
Vignesh Raghavendra923eeaf2021-05-10 20:06:04 +0530318 *fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id);
Vignesh Raghavendra9a7ad5e2020-07-06 13:26:23 +0530319 if (!(*fwd_ring))
320 return -ENODEV;
321
Vignesh Raghavendra923eeaf2021-05-10 20:06:04 +0530322 *compl_ring = k3_nav_ringacc_request_ring(ringacc, compl_id);
Vignesh Raghavendra9a7ad5e2020-07-06 13:26:23 +0530323 if (!(*compl_ring)) {
324 k3_nav_ringacc_ring_free(*fwd_ring);
325 ret = -ENODEV;
326 }
327
328 return ret;
329}
330
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530331static void k3_ringacc_ring_reset_sci(struct k3_nav_ring *ring)
332{
333 struct k3_nav_ringacc *ringacc = ring->parent;
334 int ret;
335
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530336 if (IS_ENABLED(CONFIG_K3_DM_FW))
337 return k3_ringacc_ring_reset_raw(ring);
338
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530339 ret = ringacc->tisci_ring_ops->config(
340 ringacc->tisci,
341 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID,
342 ringacc->tisci_dev_id,
343 ring->ring_id,
344 0,
345 0,
346 ring->size,
347 0,
348 0,
349 0);
350 if (ret)
351 dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
352 ret, ring->ring_id);
353}
354
355void k3_nav_ringacc_ring_reset(struct k3_nav_ring *ring)
356{
357 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
358 return;
359
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530360 memset(&ring->state, 0, sizeof(ring->state));
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530361
362 k3_ringacc_ring_reset_sci(ring);
363}
364
365static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_nav_ring *ring,
366 enum k3_nav_ring_mode mode)
367{
368 struct k3_nav_ringacc *ringacc = ring->parent;
369 int ret;
370
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530371 if (IS_ENABLED(CONFIG_K3_DM_FW))
372 return k3_ringacc_ring_reconfig_qmode_raw(ring, mode);
373
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530374 ret = ringacc->tisci_ring_ops->config(
375 ringacc->tisci,
376 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID,
377 ringacc->tisci_dev_id,
378 ring->ring_id,
379 0,
380 0,
381 0,
382 mode,
383 0,
384 0);
385 if (ret)
386 dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
387 ret, ring->ring_id);
388}
389
390void k3_nav_ringacc_ring_reset_dma(struct k3_nav_ring *ring, u32 occ)
391{
392 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
393 return;
394
Vignesh Raghavendra4fa240e2019-08-30 11:02:24 +0530395 if (!ring->parent->dma_ring_reset_quirk) {
396 k3_nav_ringacc_ring_reset(ring);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530397 return;
Vignesh Raghavendra4fa240e2019-08-30 11:02:24 +0530398 }
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530399
400 if (!occ)
401 occ = ringacc_readl(&ring->rt->occ);
402
403 if (occ) {
404 u32 db_ring_cnt, db_ring_cnt_cur;
405
406 pr_debug("%s %u occ: %u\n", __func__,
407 ring->ring_id, occ);
408 /* 2. Reset the ring */
409 k3_ringacc_ring_reset_sci(ring);
410
411 /*
412 * 3. Setup the ring in ring/doorbell mode
413 * (if not already in this mode)
414 */
415 if (ring->mode != K3_NAV_RINGACC_RING_MODE_RING)
416 k3_ringacc_ring_reconfig_qmode_sci(
417 ring, K3_NAV_RINGACC_RING_MODE_RING);
418 /*
Michal Simekcc046dc2024-04-16 08:55:19 +0200419 * 4. Ring the doorbell 2**22 - ringOcc times.
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530420 * This will wrap the internal UDMAP ring state occupancy
421 * counter (which is 21-bits wide) to 0.
422 */
423 db_ring_cnt = (1U << 22) - occ;
424
425 while (db_ring_cnt != 0) {
426 /*
427 * Ring the doorbell with the maximum count each
428 * iteration if possible to minimize the total
429 * of writes
430 */
431 if (db_ring_cnt > KNAV_RINGACC_MAX_DB_RING_CNT)
432 db_ring_cnt_cur = KNAV_RINGACC_MAX_DB_RING_CNT;
433 else
434 db_ring_cnt_cur = db_ring_cnt;
435
436 writel(db_ring_cnt_cur, &ring->rt->db);
437 db_ring_cnt -= db_ring_cnt_cur;
438 }
439
440 /* 5. Restore the original ring mode (if not ring mode) */
441 if (ring->mode != K3_NAV_RINGACC_RING_MODE_RING)
442 k3_ringacc_ring_reconfig_qmode_sci(ring, ring->mode);
443 }
444
445 /* 2. Reset the ring */
446 k3_nav_ringacc_ring_reset(ring);
447}
448
449static void k3_ringacc_ring_free_sci(struct k3_nav_ring *ring)
450{
451 struct k3_nav_ringacc *ringacc = ring->parent;
452 int ret;
453
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530454 if (IS_ENABLED(CONFIG_K3_DM_FW))
455 return k3_ringacc_ring_free_raw(ring);
456
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530457 ret = ringacc->tisci_ring_ops->config(
458 ringacc->tisci,
459 TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
460 ringacc->tisci_dev_id,
461 ring->ring_id,
462 0,
463 0,
464 0,
465 0,
466 0,
467 0);
468 if (ret)
469 dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
470 ret, ring->ring_id);
471}
472
473int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring)
474{
475 struct k3_nav_ringacc *ringacc;
476
477 if (!ring)
478 return -EINVAL;
479
480 ringacc = ring->parent;
481
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530482 /*
483 * k3_dmaring: rings shared memory and configuration, only forward ring is
484 * configured and reverse ring considered as slave.
485 */
486 if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
487 return 0;
488
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530489 pr_debug("%s flags: 0x%08x\n", __func__, ring->flags);
490
491 if (!test_bit(ring->ring_id, ringacc->rings_inuse))
492 return -EINVAL;
493
494 if (--ring->use_count)
495 goto out;
496
497 if (!(ring->flags & KNAV_RING_FLAG_BUSY))
498 goto no_init;
499
500 k3_ringacc_ring_free_sci(ring);
501
502 dma_free_coherent(ringacc->dev,
503 ring->size * (4 << ring->elm_size),
504 ring->ring_mem_virt, ring->ring_mem_dma);
505 ring->flags &= ~KNAV_RING_FLAG_BUSY;
506 ring->ops = NULL;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530507
508no_init:
509 clear_bit(ring->ring_id, ringacc->rings_inuse);
510
511 module_put(ringacc->dev->driver->owner);
512
513out:
514 return 0;
515}
516
517u32 k3_nav_ringacc_get_ring_id(struct k3_nav_ring *ring)
518{
519 if (!ring)
520 return -EINVAL;
521
522 return ring->ring_id;
523}
524
525static int k3_nav_ringacc_ring_cfg_sci(struct k3_nav_ring *ring)
526{
527 struct k3_nav_ringacc *ringacc = ring->parent;
528 u32 ring_idx;
529 int ret;
530
531 if (!ringacc->tisci)
532 return -EINVAL;
533
534 ring_idx = ring->ring_id;
535 ret = ringacc->tisci_ring_ops->config(
536 ringacc->tisci,
537 TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
538 ringacc->tisci_dev_id,
539 ring_idx,
540 lower_32_bits(ring->ring_mem_dma),
541 upper_32_bits(ring->ring_mem_dma),
542 ring->size,
543 ring->mode,
544 ring->elm_size,
545 0);
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530546 if (ret) {
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530547 dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
548 ret, ring_idx);
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530549 return ret;
550 }
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530551
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530552 /*
553 * Above TI SCI call handles firewall configuration, cfg
554 * register configuration still has to be done locally in
555 * absence of RM services.
556 */
557 if (IS_ENABLED(CONFIG_K3_DM_FW))
558 k3_nav_ringacc_ring_cfg_raw(ring);
559
560 return 0;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530561}
562
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530563static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg)
564{
565 struct k3_nav_ringacc *ringacc;
566 struct k3_nav_ring *reverse_ring;
567 int ret = 0;
568
569 if (cfg->elm_size != K3_NAV_RINGACC_RING_ELSIZE_8 ||
570 cfg->mode != K3_NAV_RINGACC_RING_MODE_RING ||
571 cfg->size & ~K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK)
572 return -EINVAL;
573
574 ringacc = ring->parent;
575
576 /*
577 * k3_dmaring: rings shared memory and configuration, only forward ring is
578 * configured and reverse ring considered as slave.
579 */
580 if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
581 return 0;
582
583 if (!test_bit(ring->ring_id, ringacc->rings_inuse))
584 return -EINVAL;
585
586 ring->size = cfg->size;
587 ring->elm_size = cfg->elm_size;
588 ring->mode = cfg->mode;
589 memset(&ring->state, 0, sizeof(ring->state));
590
591 ring->ops = &k3_dmaring_fwd_ring_ops;
592
593 ring->ring_mem_virt =
594 dma_alloc_coherent(ring->size * (4 << ring->elm_size),
595 (unsigned long *)&ring->ring_mem_dma);
596 if (!ring->ring_mem_virt) {
597 dev_err(ringacc->dev, "Failed to alloc ring mem\n");
598 ret = -ENOMEM;
599 goto err_free_ops;
600 }
601
602 ret = k3_nav_ringacc_ring_cfg_sci(ring);
603 if (ret)
604 goto err_free_mem;
605
606 ring->flags |= KNAV_RING_FLAG_BUSY;
607
608 /* k3_dmaring: configure reverse ring */
609 reverse_ring = &ringacc->rings[ring->ring_id + ringacc->num_rings];
610 reverse_ring->size = cfg->size;
611 reverse_ring->elm_size = cfg->elm_size;
612 reverse_ring->mode = cfg->mode;
613 memset(&reverse_ring->state, 0, sizeof(reverse_ring->state));
614 reverse_ring->ops = &k3_dmaring_reverse_ring_ops;
615
616 reverse_ring->ring_mem_virt = ring->ring_mem_virt;
617 reverse_ring->ring_mem_dma = ring->ring_mem_dma;
618 reverse_ring->flags |= KNAV_RING_FLAG_BUSY;
619
620 return 0;
621
622err_free_mem:
623 dma_free_coherent(ringacc->dev,
624 ring->size * (4 << ring->elm_size),
625 ring->ring_mem_virt,
626 ring->ring_mem_dma);
627err_free_ops:
628 ring->ops = NULL;
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530629 return ret;
630}
631
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530632int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
633 struct k3_nav_ring_cfg *cfg)
634{
635 struct k3_nav_ringacc *ringacc = ring->parent;
636 int ret = 0;
637
638 if (!ring || !cfg)
639 return -EINVAL;
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530640
641 if (ringacc->dual_ring)
642 return k3_dmaring_ring_cfg(ring, cfg);
643
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530644 if (cfg->elm_size > K3_NAV_RINGACC_RING_ELSIZE_256 ||
645 cfg->mode > K3_NAV_RINGACC_RING_MODE_QM ||
646 cfg->size & ~KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK ||
647 !test_bit(ring->ring_id, ringacc->rings_inuse))
648 return -EINVAL;
649
650 if (ring->use_count != 1)
651 return 0;
652
653 ring->size = cfg->size;
654 ring->elm_size = cfg->elm_size;
655 ring->mode = cfg->mode;
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530656 memset(&ring->state, 0, sizeof(ring->state));
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530657
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530658 switch (ring->mode) {
659 case K3_NAV_RINGACC_RING_MODE_RING:
660 ring->ops = &k3_nav_mode_ring_ops;
661 break;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530662 default:
663 ring->ops = NULL;
664 ret = -EINVAL;
Vignesh Raghavendra923eeaf2021-05-10 20:06:04 +0530665 goto err_free_ops;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530666 };
667
668 ring->ring_mem_virt =
669 dma_zalloc_coherent(ringacc->dev,
670 ring->size * (4 << ring->elm_size),
671 &ring->ring_mem_dma, GFP_KERNEL);
672 if (!ring->ring_mem_virt) {
673 dev_err(ringacc->dev, "Failed to alloc ring mem\n");
674 ret = -ENOMEM;
675 goto err_free_ops;
676 }
677
678 ret = k3_nav_ringacc_ring_cfg_sci(ring);
679
680 if (ret)
681 goto err_free_mem;
682
683 ring->flags |= KNAV_RING_FLAG_BUSY;
684 ring->flags |= (cfg->flags & K3_NAV_RINGACC_RING_SHARED) ?
685 K3_NAV_RING_FLAG_SHARED : 0;
686
687 return 0;
688
689err_free_mem:
690 dma_free_coherent(ringacc->dev,
691 ring->size * (4 << ring->elm_size),
692 ring->ring_mem_virt,
693 ring->ring_mem_dma);
694err_free_ops:
695 ring->ops = NULL;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530696 return ret;
697}
698
699u32 k3_nav_ringacc_ring_get_size(struct k3_nav_ring *ring)
700{
701 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
702 return -EINVAL;
703
704 return ring->size;
705}
706
707u32 k3_nav_ringacc_ring_get_free(struct k3_nav_ring *ring)
708{
709 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
710 return -EINVAL;
711
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530712 if (!ring->state.free)
713 ring->state.free = ring->size - ringacc_readl(&ring->rt->occ);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530714
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530715 return ring->state.free;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530716}
717
718u32 k3_nav_ringacc_ring_get_occ(struct k3_nav_ring *ring)
719{
720 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
721 return -EINVAL;
722
723 return ringacc_readl(&ring->rt->occ);
724}
725
726u32 k3_nav_ringacc_ring_is_full(struct k3_nav_ring *ring)
727{
728 return !k3_nav_ringacc_ring_get_free(ring);
729}
730
731enum k3_ringacc_access_mode {
732 K3_RINGACC_ACCESS_MODE_PUSH_HEAD,
733 K3_RINGACC_ACCESS_MODE_POP_HEAD,
734 K3_RINGACC_ACCESS_MODE_PUSH_TAIL,
735 K3_RINGACC_ACCESS_MODE_POP_TAIL,
736 K3_RINGACC_ACCESS_MODE_PEEK_HEAD,
737 K3_RINGACC_ACCESS_MODE_PEEK_TAIL,
738};
739
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530740static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem)
741{
742 void *elem_ptr;
743 u32 elem_idx;
744
745 /*
746 * k3_dmaring: forward ring is always tied DMA channel and HW does not
747 * maintain any state data required for POP operation and its unknown
748 * how much elements were consumed by HW. So, to actually
749 * do POP, the read pointer has to be recalculated every time.
750 */
751 ring->state.occ = k3_nav_ringacc_ring_read_occ(ring);
752 if (ring->state.windex >= ring->state.occ)
753 elem_idx = ring->state.windex - ring->state.occ;
754 else
755 elem_idx = ring->size - (ring->state.occ - ring->state.windex);
756
757 elem_ptr = k3_nav_ringacc_get_elm_addr(ring, elem_idx);
758 invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
759 ALIGN((unsigned long)ring->ring_mem_virt +
760 ring->size * (4 << ring->elm_size),
761 ARCH_DMA_MINALIGN));
762
763 memcpy(elem, elem_ptr, (4 << ring->elm_size));
764
765 ring->state.occ--;
766 writel(-1, &ring->rt->db);
767
768 dev_dbg(ring->parent->dev, "%s: occ%d Windex%d Rindex%d pos_ptr%px\n",
769 __func__, ring->state.occ, ring->state.windex, elem_idx,
770 elem_ptr);
771 return 0;
772}
773
774static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem)
775{
776 void *elem_ptr;
777
778 elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->state.rindex);
779
780 if (ring->state.occ) {
781 invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
782 ALIGN((unsigned long)ring->ring_mem_virt +
783 ring->size * (4 << ring->elm_size),
784 ARCH_DMA_MINALIGN));
785
786 memcpy(elem, elem_ptr, (4 << ring->elm_size));
787 ring->state.rindex = (ring->state.rindex + 1) % ring->size;
788 ring->state.occ--;
789 writel(-1 & K3_DMARING_RING_RT_DB_ENTRY_MASK, &ring->rt->db);
790 }
791
792 dev_dbg(ring->parent->dev, "%s: occ%d index%d pos_ptr%px\n",
793 __func__, ring->state.occ, ring->state.rindex, elem_ptr);
794 return 0;
795}
796
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530797static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem)
798{
799 void *elem_ptr;
800
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530801 elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->state.windex);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530802
803 memcpy(elem_ptr, elem, (4 << ring->elm_size));
804
Vignesh Raghavendra197e5c22019-12-09 10:25:33 +0530805 flush_dcache_range((unsigned long)ring->ring_mem_virt,
806 ALIGN((unsigned long)ring->ring_mem_virt +
807 ring->size * (4 << ring->elm_size),
808 ARCH_DMA_MINALIGN));
809
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530810 ring->state.windex = (ring->state.windex + 1) % ring->size;
811 ring->state.free--;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530812 ringacc_writel(1, &ring->rt->db);
813
814 pr_debug("ring_push_mem: free%d index%d\n",
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530815 ring->state.free, ring->state.windex);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530816
817 return 0;
818}
819
820static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem)
821{
822 void *elem_ptr;
823
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530824 elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->state.rindex);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530825
Vignesh Raghavendra197e5c22019-12-09 10:25:33 +0530826 invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
827 ALIGN((unsigned long)ring->ring_mem_virt +
828 ring->size * (4 << ring->elm_size),
829 ARCH_DMA_MINALIGN));
830
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530831 memcpy(elem, elem_ptr, (4 << ring->elm_size));
832
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530833 ring->state.rindex = (ring->state.rindex + 1) % ring->size;
834 ring->state.occ--;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530835 ringacc_writel(-1, &ring->rt->db);
836
837 pr_debug("ring_pop_mem: occ%d index%d pos_ptr%p\n",
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530838 ring->state.occ, ring->state.rindex, elem_ptr);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530839 return 0;
840}
841
842int k3_nav_ringacc_ring_push(struct k3_nav_ring *ring, void *elem)
843{
844 int ret = -EOPNOTSUPP;
845
846 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
847 return -EINVAL;
848
849 pr_debug("ring_push%d: free%d index%d\n",
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530850 ring->ring_id, ring->state.free, ring->state.windex);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530851
852 if (k3_nav_ringacc_ring_is_full(ring))
853 return -ENOMEM;
854
855 if (ring->ops && ring->ops->push_tail)
856 ret = ring->ops->push_tail(ring, elem);
857
858 return ret;
859}
860
861int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem)
862{
863 int ret = -EOPNOTSUPP;
864
865 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
866 return -EINVAL;
867
868 pr_debug("ring_push_head: free%d index%d\n",
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530869 ring->state.free, ring->state.windex);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530870
871 if (k3_nav_ringacc_ring_is_full(ring))
872 return -ENOMEM;
873
874 if (ring->ops && ring->ops->push_head)
875 ret = ring->ops->push_head(ring, elem);
876
877 return ret;
878}
879
880int k3_nav_ringacc_ring_pop(struct k3_nav_ring *ring, void *elem)
881{
882 int ret = -EOPNOTSUPP;
883
884 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
885 return -EINVAL;
886
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530887 if (!ring->state.occ)
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530888 k3_nav_ringacc_ring_update_occ(ring);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530889
890 pr_debug("ring_pop%d: occ%d index%d\n",
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530891 ring->ring_id, ring->state.occ, ring->state.rindex);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530892
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530893 if (!ring->state.occ && !ring->state.tdown_complete)
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530894 return -ENODATA;
895
896 if (ring->ops && ring->ops->pop_head)
897 ret = ring->ops->pop_head(ring, elem);
898
899 return ret;
900}
901
902int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem)
903{
904 int ret = -EOPNOTSUPP;
905
906 if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
907 return -EINVAL;
908
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530909 if (!ring->state.occ)
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530910 k3_nav_ringacc_ring_update_occ(ring);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530911
912 pr_debug("ring_pop_tail: occ%d index%d\n",
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530913 ring->state.occ, ring->state.rindex);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530914
Vignesh Raghavendra91b43352020-07-06 13:26:22 +0530915 if (!ring->state.occ)
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530916 return -ENODATA;
917
918 if (ring->ops && ring->ops->pop_tail)
919 ret = ring->ops->pop_tail(ring, elem);
920
921 return ret;
922}
923
924static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
925{
926 struct udevice *dev = ringacc->dev;
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530927 struct udevice *devp = dev;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530928 struct udevice *tisci_dev = NULL;
929 int ret;
930
931 ringacc->num_rings = dev_read_u32_default(dev, "ti,num-rings", 0);
932 if (!ringacc->num_rings) {
933 dev_err(dev, "ti,num-rings read failure %d\n", ret);
934 return -EINVAL;
935 }
936
937 ringacc->dma_ring_reset_quirk =
938 dev_read_bool(dev, "ti,dma-ring-reset-quirk");
939
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530940 ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, devp,
Vignesh Raghavendrae414d152019-12-09 10:25:34 +0530941 "ti,sci", &tisci_dev);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530942 if (ret) {
943 pr_debug("TISCI RA RM get failed (%d)\n", ret);
944 ringacc->tisci = NULL;
945 return -ENODEV;
946 }
947 ringacc->tisci = (struct ti_sci_handle *)
948 (ti_sci_get_handle_from_sysfw(tisci_dev));
949
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530950 ret = dev_read_u32_default(devp, "ti,sci", 0);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530951 if (!ret) {
952 dev_err(dev, "TISCI RA RM disabled\n");
953 ringacc->tisci = NULL;
954 return ret;
955 }
956
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +0530957 ret = dev_read_u32(devp, "ti,sci-dev-id", &ringacc->tisci_dev_id);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530958 if (ret) {
959 dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
960 ringacc->tisci = NULL;
961 return ret;
962 }
963
964 ringacc->rm_gp_range = devm_ti_sci_get_of_resource(
965 ringacc->tisci, dev,
966 ringacc->tisci_dev_id,
967 "ti,sci-rm-range-gp-rings");
968 if (IS_ERR(ringacc->rm_gp_range))
969 ret = PTR_ERR(ringacc->rm_gp_range);
970
971 return 0;
972}
973
Vignesh Raghavendrab627aad2020-07-06 13:26:24 +0530974static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc)
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530975{
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530976 void __iomem *base_cfg, *base_rt;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530977 int ret, i;
978
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530979 ret = k3_nav_ringacc_probe_dt(ringacc);
980 if (ret)
981 return ret;
982
Vignesh Raghavendraae067e52021-06-07 19:47:52 +0530983 base_cfg = dev_remap_addr_name(dev, "cfg");
984 pr_debug("cfg %p\n", base_cfg);
985 if (!base_cfg)
986 return -EINVAL;
987
Matthias Schiffer47331932023-09-27 15:33:34 +0200988 base_rt = dev_read_addr_name_ptr(dev, "rt");
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530989 pr_debug("rt %p\n", base_rt);
Matthias Schiffer47331932023-09-27 15:33:34 +0200990 if (!base_rt)
991 return -EINVAL;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530992
Grygorii Strashko1c5258f2019-02-05 17:31:22 +0530993 ringacc->rings = devm_kzalloc(dev,
994 sizeof(*ringacc->rings) *
995 ringacc->num_rings,
996 GFP_KERNEL);
997 ringacc->rings_inuse = devm_kcalloc(dev,
998 BITS_TO_LONGS(ringacc->num_rings),
999 sizeof(unsigned long), GFP_KERNEL);
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301000
Vignesh Raghavendra923eeaf2021-05-10 20:06:04 +05301001 if (!ringacc->rings || !ringacc->rings_inuse)
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301002 return -ENOMEM;
1003
1004 for (i = 0; i < ringacc->num_rings; i++) {
Vignesh Raghavendraae067e52021-06-07 19:47:52 +05301005 ringacc->rings[i].cfg = base_cfg +
1006 KNAV_RINGACC_CFG_REGS_STEP * i;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301007 ringacc->rings[i].rt = base_rt +
1008 KNAV_RINGACC_RT_REGS_STEP * i;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301009 ringacc->rings[i].parent = ringacc;
1010 ringacc->rings[i].ring_id = i;
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301011 }
1012 dev_set_drvdata(dev, ringacc);
1013
1014 ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops;
1015
1016 list_add_tail(&ringacc->list, &k3_nav_ringacc_list);
1017
1018 dev_info(dev, "Ring Accelerator probed rings:%u, gp-rings[%u,%u] sci-dev-id:%u\n",
1019 ringacc->num_rings,
1020 ringacc->rm_gp_range->desc[0].start,
1021 ringacc->rm_gp_range->desc[0].num,
1022 ringacc->tisci_dev_id);
1023 dev_info(dev, "dma-ring-reset-quirk: %s\n",
1024 ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301025 return 0;
1026}
1027
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +05301028struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
1029 struct k3_ringacc_init_data *data)
1030{
1031 struct k3_nav_ringacc *ringacc;
1032 void __iomem *base_rt;
1033 int i;
1034
1035 ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
1036 if (!ringacc)
1037 return ERR_PTR(-ENOMEM);
1038
1039 ringacc->dual_ring = true;
1040
1041 ringacc->dev = dev;
1042 ringacc->num_rings = data->num_rings;
1043 ringacc->tisci = data->tisci;
1044 ringacc->tisci_dev_id = data->tisci_dev_id;
1045
Matthias Schiffer47331932023-09-27 15:33:34 +02001046 base_rt = dev_read_addr_name_ptr(dev, "ringrt");
1047 if (!base_rt)
1048 return ERR_PTR(-EINVAL);
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +05301049
1050 ringacc->rings = devm_kzalloc(dev,
1051 sizeof(*ringacc->rings) *
1052 ringacc->num_rings * 2,
1053 GFP_KERNEL);
1054 ringacc->rings_inuse = devm_kcalloc(dev,
1055 BITS_TO_LONGS(ringacc->num_rings),
1056 sizeof(unsigned long), GFP_KERNEL);
1057
1058 if (!ringacc->rings || !ringacc->rings_inuse)
1059 return ERR_PTR(-ENOMEM);
1060
1061 for (i = 0; i < ringacc->num_rings; i++) {
1062 struct k3_nav_ring *ring = &ringacc->rings[i];
1063
1064 ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i;
1065 ring->parent = ringacc;
1066 ring->ring_id = i;
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +05301067
1068 ring = &ringacc->rings[ringacc->num_rings + i];
1069 ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i +
1070 K3_DMARING_RING_RT_REGS_REVERSE_OFS;
1071 ring->parent = ringacc;
1072 ring->ring_id = i;
Vignesh Raghavendra6ca48602021-05-10 20:06:03 +05301073 ring->flags = K3_NAV_RING_FLAG_REVERSE;
1074 }
1075
1076 ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops;
1077
1078 dev_info(dev, "k3_dmaring Ring probed rings:%u, sci-dev-id:%u\n",
1079 ringacc->num_rings,
1080 ringacc->tisci_dev_id);
1081 dev_info(dev, "dma-ring-reset-quirk: %s\n",
1082 ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
1083
1084 return ringacc;
1085}
1086
Vignesh Raghavendrab627aad2020-07-06 13:26:24 +05301087struct ringacc_match_data {
1088 struct k3_nav_ringacc_ops ops;
1089};
1090
1091static struct ringacc_match_data k3_nav_ringacc_data = {
1092 .ops = {
1093 .init = k3_nav_ringacc_init,
1094 },
1095};
1096
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301097static const struct udevice_id knav_ringacc_ids[] = {
Vignesh Raghavendrab627aad2020-07-06 13:26:24 +05301098 { .compatible = "ti,am654-navss-ringacc", .data = (ulong)&k3_nav_ringacc_data, },
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301099 {},
1100};
1101
Vignesh Raghavendrab627aad2020-07-06 13:26:24 +05301102static int k3_nav_ringacc_probe(struct udevice *dev)
1103{
1104 struct k3_nav_ringacc *ringacc;
1105 int ret;
1106 const struct ringacc_match_data *match_data;
1107
1108 match_data = (struct ringacc_match_data *)dev_get_driver_data(dev);
1109
1110 ringacc = dev_get_priv(dev);
1111 if (!ringacc)
1112 return -ENOMEM;
1113
1114 ringacc->dev = dev;
1115 ringacc->ops = &match_data->ops;
1116 ret = ringacc->ops->init(dev, ringacc);
1117 if (ret)
1118 return ret;
1119
1120 return 0;
1121}
1122
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301123U_BOOT_DRIVER(k3_navss_ringacc) = {
1124 .name = "k3-navss-ringacc",
1125 .id = UCLASS_MISC,
1126 .of_match = knav_ringacc_ids,
1127 .probe = k3_nav_ringacc_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001128 .priv_auto = sizeof(struct k3_nav_ringacc),
Grygorii Strashko1c5258f2019-02-05 17:31:22 +05301129};