| commit | 197e5c2954f07a27d24c06fdafa49742e642d6d5 | [log] [tgz] |
|---|---|---|
| author | Vignesh Raghavendra <vigneshr@ti.com> | Mon Dec 09 10:25:33 2019 +0530 |
| committer | Lokesh Vutla <lokeshvutla@ti.com> | Mon Jan 20 10:10:28 2020 +0530 |
| tree | 8b1b5c2795d425d974ea899551d3111a85a37260 | |
| parent | c41068658a0c7bac7dfc84abf57a4c459b604e66 [diff] |
soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop Flush caches when pushing an element to ring and invalidate caches when popping an element from ring in Exposed Ring mode. Otherwise DMA transfers don't work properly in R5 SPL (with caches enabled) where the core is not in coherency domain. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>