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git01.mediatek.com / filogic / uboot / 8c8fb8561efde9501c98f469c3e2700e861663fe / . / arch / arm / dts / k3-am625-sk-u-boot.dtsi
blob: 7ae5e01f7c7fbd19ec4a936c23a2f3cbaa9017e4 [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM625 SK dts file for SPLs
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
Neha Malcom Francis8f8f4fc2023-07-22 00:14:38 +0530[diff] [blame]7#include "k3-am625-sk-binman.dtsi"
8
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]12 tick-timer = &main_timer0;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]13 };
14
15 aliases {
16 mmc1 = &sdhci1;
17 };
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]18
19 memory@80000000 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]20 bootph-all;
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]21 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]22};
23
Roger Quadros301ebec2023-09-29 16:46:46 +0300[diff] [blame]24&main_conf {
25 bootph-all;
26};
27
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]28&cbass_main {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]29 bootph-all;
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]30};
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]31
Nishanth Menone17596d2023-07-27 04:03:31 -0500[diff] [blame]32&main_timer0 {
33 clock-frequency = <25000000>;
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]34 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]35};
36
37&dmss {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]38 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]39};
40
41&secure_proxy_main {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]42 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]43};
44
45&dmsc {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]46 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]47};
48
49&k3_pds {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]50 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]51};
52
53&k3_clks {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]54 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]55};
56
57&k3_reset {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]58 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]59};
60
61&wkup_conf {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]62 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]63};
64
65&chipid {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]66 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]67};
68
69&main_pmx0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]70 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]71};
72
73&main_uart0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]74 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]75};
76
77&main_uart0_pins_default {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]78 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]79};
80
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]81&cbass_mcu {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]82 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]83};
84
85&cbass_wakeup {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]86 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]87};
88
89&mcu_pmx0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]90 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]91};
92
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]93&sdhci1 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]94 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]95};
96
97&main_mmc1_pins_default {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]98 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]99};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]100
101&fss {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]102 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]103};
104
105&ospi0_pins_default {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]106 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]107};
108
109&ospi0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]110 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]111
112 flash@0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]113 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]114
115 partitions {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]116 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]117
118 partition@3fc0000 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]119 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]120 };
121 };
122 };
123};
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]124
Roger Quadros301ebec2023-09-29 16:46:46 +0300[diff] [blame]125&inta_main_dmss {
126 bootph-all;
127};
128
Siddharth Vadapalliecd27822023-10-28 20:36:01 +0300[diff] [blame]129&main_bcdma {
130 reg = <0x00 0x485c0100 0x00 0x100>,
131 <0x00 0x4c000000 0x00 0x20000>,
132 <0x00 0x4a820000 0x00 0x20000>,
133 <0x00 0x4aa40000 0x00 0x20000>,
134 <0x00 0x4bc00000 0x00 0x100000>,
135 <0x00 0x48600000 0x00 0x8000>,
136 <0x00 0x484a4000 0x00 0x2000>,
137 <0x00 0x484c2000 0x00 0x2000>;
138 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
139 "ringrt" , "cfg", "tchan", "rchan";
140};
141
Roger Quadros301ebec2023-09-29 16:46:46 +0300[diff] [blame]142&main_pktdma {
Siddharth Vadapalliecd27822023-10-28 20:36:01 +0300[diff] [blame]143 reg = <0x00 0x485c0000 0x00 0x100>,
144 <0x00 0x4a800000 0x00 0x20000>,
145 <0x00 0x4aa00000 0x00 0x20000>,
146 <0x00 0x4b800000 0x00 0x200000>,
147 <0x00 0x485e0000 0x00 0x10000>,
148 <0x00 0x484a0000 0x00 0x2000>,
149 <0x00 0x484c0000 0x00 0x2000>,
150 <0x00 0x48430000 0x00 0x1000>;
151 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
152 "cfg", "tchan", "rchan", "rflow";
Roger Quadros301ebec2023-09-29 16:46:46 +0300[diff] [blame]153 bootph-all;
154};
155
156&cpsw3g_mdio {
157 bootph-all;
158};
159
160&cpsw3g_phy0 {
161 bootph-all;
162};
163
164&cpsw3g_phy1 {
165 bootph-all;
166};
167
168&main_rgmii1_pins_default {
169 bootph-all;
170};
171
172&main_rgmii2_pins_default {
173 bootph-all;
174};
175
176&phy_gmii_sel {
177 bootph-all;
178};
179
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]180&cpsw3g {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]181 bootph-all;
Roger Quadros301ebec2023-09-29 16:46:46 +0300[diff] [blame]182 ethernet-ports {
183 bootph-all;
184 };
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]185};
186
187&cpsw_port1 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300[diff] [blame]188 bootph-all;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]189};
190
191&cpsw_port2 {
192 status = "disabled";
193};