Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | ||||
3 | * Common AM625 SK dts file for SPLs | ||||
4 | * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ | ||||
5 | */ | ||||
6 | |||||
Neha Malcom Francis | 8f8f4fc | 2023-07-22 00:14:38 +0530 | [diff] [blame] | 7 | #include "k3-am625-sk-binman.dtsi" |
8 | |||||
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 9 | / { |
10 | chosen { | ||||
11 | stdout-path = "serial2:115200n8"; | ||||
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 12 | tick-timer = &main_timer0; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 13 | }; |
14 | |||||
15 | aliases { | ||||
16 | mmc1 = &sdhci1; | ||||
17 | }; | ||||
Georgi Vlaev | e9c68bf | 2022-06-14 17:45:31 +0300 | [diff] [blame] | 18 | |
19 | memory@80000000 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 20 | bootph-all; |
Georgi Vlaev | e9c68bf | 2022-06-14 17:45:31 +0300 | [diff] [blame] | 21 | }; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 22 | }; |
23 | |||||
Roger Quadros | 301ebec | 2023-09-29 16:46:46 +0300 | [diff] [blame^] | 24 | &main_conf { |
25 | bootph-all; | ||||
26 | }; | ||||
27 | |||||
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 28 | &cbass_main { |
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 29 | bootph-all; |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 30 | }; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 31 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 32 | &main_timer0 { |
33 | clock-frequency = <25000000>; | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 34 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 35 | }; |
36 | |||||
37 | &dmss { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 38 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 39 | }; |
40 | |||||
41 | &secure_proxy_main { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 42 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 43 | }; |
44 | |||||
45 | &dmsc { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 46 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 47 | }; |
48 | |||||
49 | &k3_pds { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 50 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 51 | }; |
52 | |||||
53 | &k3_clks { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 54 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 55 | }; |
56 | |||||
57 | &k3_reset { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 58 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 59 | }; |
60 | |||||
61 | &wkup_conf { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 62 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 63 | }; |
64 | |||||
65 | &chipid { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 66 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 67 | }; |
68 | |||||
69 | &main_pmx0 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 70 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 71 | }; |
72 | |||||
73 | &main_uart0 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 74 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 75 | }; |
76 | |||||
77 | &main_uart0_pins_default { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 78 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 79 | }; |
80 | |||||
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 81 | &cbass_mcu { |
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 82 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 83 | }; |
84 | |||||
85 | &cbass_wakeup { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 86 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 87 | }; |
88 | |||||
89 | &mcu_pmx0 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 90 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 91 | }; |
92 | |||||
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 93 | &sdhci1 { |
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 94 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 95 | }; |
96 | |||||
97 | &main_mmc1_pins_default { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 98 | bootph-all; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 99 | }; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 100 | |
101 | &fss { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 102 | bootph-all; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 103 | }; |
104 | |||||
105 | &ospi0_pins_default { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 106 | bootph-all; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 107 | }; |
108 | |||||
109 | &ospi0 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 110 | bootph-all; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 111 | |
112 | flash@0 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 113 | bootph-all; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 114 | |
115 | partitions { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 116 | bootph-all; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 117 | |
118 | partition@3fc0000 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 119 | bootph-all; |
Dhruva Gole | 0f33ef2 | 2022-10-27 20:23:10 +0530 | [diff] [blame] | 120 | }; |
121 | }; | ||||
122 | }; | ||||
123 | }; | ||||
Sjoerd Simons | 7fb6d4a | 2022-12-20 16:21:45 +0100 | [diff] [blame] | 124 | |
Roger Quadros | 301ebec | 2023-09-29 16:46:46 +0300 | [diff] [blame^] | 125 | &inta_main_dmss { |
126 | bootph-all; | ||||
127 | }; | ||||
128 | |||||
129 | &main_pktdma { | ||||
130 | bootph-all; | ||||
131 | }; | ||||
132 | |||||
133 | &cpsw3g_mdio { | ||||
134 | bootph-all; | ||||
135 | }; | ||||
136 | |||||
137 | &cpsw3g_phy0 { | ||||
138 | bootph-all; | ||||
139 | }; | ||||
140 | |||||
141 | &cpsw3g_phy1 { | ||||
142 | bootph-all; | ||||
143 | }; | ||||
144 | |||||
145 | &main_rgmii1_pins_default { | ||||
146 | bootph-all; | ||||
147 | }; | ||||
148 | |||||
149 | &main_rgmii2_pins_default { | ||||
150 | bootph-all; | ||||
151 | }; | ||||
152 | |||||
153 | &phy_gmii_sel { | ||||
154 | bootph-all; | ||||
155 | }; | ||||
156 | |||||
Sjoerd Simons | 7fb6d4a | 2022-12-20 16:21:45 +0100 | [diff] [blame] | 157 | &cpsw3g { |
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 158 | bootph-all; |
Roger Quadros | 301ebec | 2023-09-29 16:46:46 +0300 | [diff] [blame^] | 159 | ethernet-ports { |
160 | bootph-all; | ||||
161 | }; | ||||
Sjoerd Simons | 7fb6d4a | 2022-12-20 16:21:45 +0100 | [diff] [blame] | 162 | }; |
163 | |||||
164 | &cpsw_port1 { | ||||
Roger Quadros | c579ff3 | 2023-09-29 16:46:45 +0300 | [diff] [blame] | 165 | bootph-all; |
Sjoerd Simons | 7fb6d4a | 2022-12-20 16:21:45 +0100 | [diff] [blame] | 166 | }; |
167 | |||||
168 | &cpsw_port2 { | ||||
169 | status = "disabled"; | ||||
170 | }; |