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Nishanth Menonc5ac2c72022-05-25 13:38:48 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM625 SK dts file for SPLs
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
Neha Malcom Francis8f8f4fc2023-07-22 00:14:38 +05307#include "k3-am625-sk-binman.dtsi"
8
Nishanth Menonc5ac2c72022-05-25 13:38:48 +05309/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
Nishanth Menone17596d2023-07-27 04:03:31 -050012 tick-timer = &main_timer0;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053013 };
14
15 aliases {
16 mmc1 = &sdhci1;
17 };
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +030018
19 memory@80000000 {
Roger Quadrosc579ff32023-09-29 16:46:45 +030020 bootph-all;
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +030021 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053022};
23
Roger Quadros301ebec2023-09-29 16:46:46 +030024&main_conf {
25 bootph-all;
26};
27
Nishanth Menone17596d2023-07-27 04:03:31 -050028&cbass_main {
Roger Quadrosc579ff32023-09-29 16:46:45 +030029 bootph-all;
Nishanth Menone17596d2023-07-27 04:03:31 -050030};
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053031
Nishanth Menone17596d2023-07-27 04:03:31 -050032&main_timer0 {
33 clock-frequency = <25000000>;
Roger Quadrosc579ff32023-09-29 16:46:45 +030034 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053035};
36
37&dmss {
Roger Quadrosc579ff32023-09-29 16:46:45 +030038 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053039};
40
41&secure_proxy_main {
Roger Quadrosc579ff32023-09-29 16:46:45 +030042 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053043};
44
45&dmsc {
Roger Quadrosc579ff32023-09-29 16:46:45 +030046 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053047};
48
49&k3_pds {
Roger Quadrosc579ff32023-09-29 16:46:45 +030050 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053051};
52
53&k3_clks {
Roger Quadrosc579ff32023-09-29 16:46:45 +030054 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053055};
56
57&k3_reset {
Roger Quadrosc579ff32023-09-29 16:46:45 +030058 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053059};
60
61&wkup_conf {
Roger Quadrosc579ff32023-09-29 16:46:45 +030062 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053063};
64
65&chipid {
Roger Quadrosc579ff32023-09-29 16:46:45 +030066 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053067};
68
69&main_pmx0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +030070 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053071};
72
73&main_uart0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +030074 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053075};
76
77&main_uart0_pins_default {
Roger Quadrosc579ff32023-09-29 16:46:45 +030078 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053079};
80
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053081&cbass_mcu {
Roger Quadrosc579ff32023-09-29 16:46:45 +030082 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053083};
84
85&cbass_wakeup {
Roger Quadrosc579ff32023-09-29 16:46:45 +030086 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053087};
88
89&mcu_pmx0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +030090 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053091};
92
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053093&sdhci1 {
Roger Quadrosc579ff32023-09-29 16:46:45 +030094 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053095};
96
97&main_mmc1_pins_default {
Roger Quadrosc579ff32023-09-29 16:46:45 +030098 bootph-all;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053099};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530100
101&fss {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300102 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530103};
104
105&ospi0_pins_default {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300106 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530107};
108
109&ospi0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300110 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530111
112 flash@0 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300113 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530114
115 partitions {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300116 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530117
118 partition@3fc0000 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300119 bootph-all;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530120 };
121 };
122 };
123};
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100124
Roger Quadros301ebec2023-09-29 16:46:46 +0300125&inta_main_dmss {
126 bootph-all;
127};
128
129&main_pktdma {
130 bootph-all;
131};
132
133&cpsw3g_mdio {
134 bootph-all;
135};
136
137&cpsw3g_phy0 {
138 bootph-all;
139};
140
141&cpsw3g_phy1 {
142 bootph-all;
143};
144
145&main_rgmii1_pins_default {
146 bootph-all;
147};
148
149&main_rgmii2_pins_default {
150 bootph-all;
151};
152
153&phy_gmii_sel {
154 bootph-all;
155};
156
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100157&cpsw3g {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300158 bootph-all;
Roger Quadros301ebec2023-09-29 16:46:46 +0300159 ethernet-ports {
160 bootph-all;
161 };
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100162};
163
164&cpsw_port1 {
Roger Quadrosc579ff32023-09-29 16:46:45 +0300165 bootph-all;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100166};
167
168&cpsw_port2 {
169 status = "disabled";
170};