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git01.mediatek.com / filogic / uboot / 8c7d64f09e2650836f753137e4a52ed1b639e3b0 / . / drivers / pinctrl / renesas / pfc-r8a7796.c
blob: 90dbf3994a68c85713c1d029cf721fe1f19de5ce [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
3 * R8A7796 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]12 */
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
25
26#define CPU_ALL_PORT(fn, sfx) \
27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
39/*
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
42 */
43
44/* GPSR0 */
45#define GPSR0_15 F_(D15, IP7_11_8)
46#define GPSR0_14 F_(D14, IP7_7_4)
47#define GPSR0_13 F_(D13, IP7_3_0)
48#define GPSR0_12 F_(D12, IP6_31_28)
49#define GPSR0_11 F_(D11, IP6_27_24)
50#define GPSR0_10 F_(D10, IP6_23_20)
51#define GPSR0_9 F_(D9, IP6_19_16)
52#define GPSR0_8 F_(D8, IP6_15_12)
53#define GPSR0_7 F_(D7, IP6_11_8)
54#define GPSR0_6 F_(D6, IP6_7_4)
55#define GPSR0_5 F_(D5, IP6_3_0)
56#define GPSR0_4 F_(D4, IP5_31_28)
57#define GPSR0_3 F_(D3, IP5_27_24)
58#define GPSR0_2 F_(D2, IP5_23_20)
59#define GPSR0_1 F_(D1, IP5_19_16)
60#define GPSR0_0 F_(D0, IP5_15_12)
61
62/* GPSR1 */
63#define GPSR1_28 FM(CLKOUT)
64#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65#define GPSR1_26 F_(WE1_N, IP5_7_4)
66#define GPSR1_25 F_(WE0_N, IP5_3_0)
67#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68#define GPSR1_23 F_(RD_N, IP4_27_24)
69#define GPSR1_22 F_(BS_N, IP4_23_20)
70#define GPSR1_21 F_(CS1_N, IP4_19_16)
71#define GPSR1_20 F_(CS0_N, IP4_15_12)
72#define GPSR1_19 F_(A19, IP4_11_8)
73#define GPSR1_18 F_(A18, IP4_7_4)
74#define GPSR1_17 F_(A17, IP4_3_0)
75#define GPSR1_16 F_(A16, IP3_31_28)
76#define GPSR1_15 F_(A15, IP3_27_24)
77#define GPSR1_14 F_(A14, IP3_23_20)
78#define GPSR1_13 F_(A13, IP3_19_16)
79#define GPSR1_12 F_(A12, IP3_15_12)
80#define GPSR1_11 F_(A11, IP3_11_8)
81#define GPSR1_10 F_(A10, IP3_7_4)
82#define GPSR1_9 F_(A9, IP3_3_0)
83#define GPSR1_8 F_(A8, IP2_31_28)
84#define GPSR1_7 F_(A7, IP2_27_24)
85#define GPSR1_6 F_(A6, IP2_23_20)
86#define GPSR1_5 F_(A5, IP2_19_16)
87#define GPSR1_4 F_(A4, IP2_15_12)
88#define GPSR1_3 F_(A3, IP2_11_8)
89#define GPSR1_2 F_(A2, IP2_7_4)
90#define GPSR1_1 F_(A1, IP2_3_0)
91#define GPSR1_0 F_(A0, IP1_31_28)
92
93/* GPSR2 */
94#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100#define GPSR2_8 F_(PWM2_A, IP1_27_24)
101#define GPSR2_7 F_(PWM1_A, IP1_23_20)
102#define GPSR2_6 F_(PWM0, IP1_19_16)
103#define GPSR2_5 F_(IRQ5, IP1_15_12)
104#define GPSR2_4 F_(IRQ4, IP1_11_8)
105#define GPSR2_3 F_(IRQ3, IP1_7_4)
106#define GPSR2_2 F_(IRQ2, IP1_3_0)
107#define GPSR2_1 F_(IRQ1, IP0_31_28)
108#define GPSR2_0 F_(IRQ0, IP0_27_24)
109
110/* GPSR3 */
111#define GPSR3_15 F_(SD1_WP, IP11_23_20)
112#define GPSR3_14 F_(SD1_CD, IP11_19_16)
113#define GPSR3_13 F_(SD0_WP, IP11_15_12)
114#define GPSR3_12 F_(SD0_CD, IP11_11_8)
115#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
127
128/* GPSR4 */
129#define GPSR4_17 F_(SD3_DS, IP11_7_4)
130#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
134#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
140#define GPSR4_6 F_(SD2_DS, IP9_27_24)
141#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
145#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
147
148/* GPSR5 */
149#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152#define GPSR5_22 FM(MSIOF0_RXD)
153#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154#define GPSR5_20 FM(MSIOF0_TXD)
155#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157#define GPSR5_17 FM(MSIOF0_SCK)
158#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160#define GPSR5_14 F_(HTX0, IP13_19_16)
161#define GPSR5_13 F_(HRX0, IP13_15_12)
162#define GPSR5_12 F_(HSCK0, IP13_11_8)
163#define GPSR5_11 F_(RX2_A, IP13_7_4)
164#define GPSR5_10 F_(TX2_A, IP13_3_0)
165#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]166#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]167#define GPSR5_7 F_(CTS1_N, IP12_23_20)
168#define GPSR5_6 F_(TX1_A, IP12_19_16)
169#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]170#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]171#define GPSR5_3 F_(CTS0_N, IP12_7_4)
172#define GPSR5_2 F_(TX0, IP12_3_0)
173#define GPSR5_1 F_(RX0, IP11_31_28)
174#define GPSR5_0 F_(SCK0, IP11_27_24)
175
176/* GPSR6 */
177#define GPSR6_31 F_(GP6_31, IP18_7_4)
178#define GPSR6_30 F_(GP6_30, IP18_3_0)
179#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195#define GPSR6_13 FM(SSI_SDATA5)
196#define GPSR6_12 FM(SSI_WS5)
197#define GPSR6_11 FM(SSI_SCK5)
198#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
202#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
203#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
204#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
207#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
208#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
209
210/* GPSR7 */
211#define GPSR7_3 FM(GP7_03)
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]212#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]213#define GPSR7_1 FM(AVS2)
214#define GPSR7_0 FM(AVS1)
215
216
217/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]233#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245
246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276
277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312
313/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
314#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]321#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]325#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
335#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342
343/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
344#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Hiroyuki Yokoyama6c1828e2019-02-13 10:06:22 +0900[diff] [blame]361#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]362#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
364#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
365#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
366#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
367#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
370#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
371
372#define PINMUX_GPSR \
373\
374 GPSR6_31 \
375 GPSR6_30 \
376 GPSR6_29 \
377 GPSR1_28 GPSR6_28 \
378 GPSR1_27 GPSR6_27 \
379 GPSR1_26 GPSR6_26 \
380 GPSR1_25 GPSR5_25 GPSR6_25 \
381 GPSR1_24 GPSR5_24 GPSR6_24 \
382 GPSR1_23 GPSR5_23 GPSR6_23 \
383 GPSR1_22 GPSR5_22 GPSR6_22 \
384 GPSR1_21 GPSR5_21 GPSR6_21 \
385 GPSR1_20 GPSR5_20 GPSR6_20 \
386 GPSR1_19 GPSR5_19 GPSR6_19 \
387 GPSR1_18 GPSR5_18 GPSR6_18 \
388 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
389 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
390GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
391GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
392GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
393GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
394GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
395GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
396GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
397GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
398GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
399GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
400GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
401GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
402GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
403GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
404GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
405GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
406
407#define PINMUX_IPSR \
408\
409FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
410FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
411FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
412FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
413FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
414FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
415FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
416FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
417\
418FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
419FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
420FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
421FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
422FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
423FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
424FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
425FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
426\
427FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
428FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
429FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
430FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
431FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
432FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
433FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
434FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
435\
436FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
437FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
438FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
439FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
440FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
441FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
442FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
443FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
444\
445FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
446FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
447FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
448FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
449FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
450FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
451FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
452FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
453
454/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
455#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
456#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
457#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
458#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
459#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
460#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
461#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
462#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
463#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
464#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
465#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
466#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
467#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
468#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
469#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
470#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
471#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]472#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]473
474/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
475#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
476#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
477#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
478#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
479#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]480#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]481#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
482#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
483#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
484#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
485#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
486#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
487#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
488#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
489#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
490#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
491#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
492#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
493#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
494#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
495#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
496#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
497
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]498/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]499#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
500#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
501#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
502#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
503#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
504#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]505#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]506#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
507#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
508#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]509#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
510#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]511#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
512
513#define PINMUX_MOD_SELS \
514\
515MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
516 MOD_SEL2_30 \
517 MOD_SEL1_29_28_27 MOD_SEL2_29 \
518MOD_SEL0_28_27 MOD_SEL2_28_27 \
519MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
520 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
521MOD_SEL0_23 MOD_SEL1_23_22_21 \
522MOD_SEL0_22 MOD_SEL2_22 \
523MOD_SEL0_21 MOD_SEL2_21 \
524MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
525MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
526MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
527 MOD_SEL2_17 \
528MOD_SEL0_16 MOD_SEL1_16 \
529 MOD_SEL1_15_14 \
530MOD_SEL0_14_13 \
531 MOD_SEL1_13 \
532MOD_SEL0_12 MOD_SEL1_12 \
533MOD_SEL0_11 MOD_SEL1_11 \
534MOD_SEL0_10 MOD_SEL1_10 \
535MOD_SEL0_9_8 MOD_SEL1_9 \
536MOD_SEL0_7_6 \
537 MOD_SEL1_6 \
538MOD_SEL0_5 MOD_SEL1_5 \
539MOD_SEL0_4_3 MOD_SEL1_4 \
540 MOD_SEL1_3 \
541 MOD_SEL1_2 \
542 MOD_SEL1_1 \
543 MOD_SEL1_0 MOD_SEL2_0
544
545/*
546 * These pins are not able to be muxed but have other properties
547 * that can be set, such as drive-strength or pull-up/pull-down enable.
548 */
549#define PINMUX_STATIC \
550 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
551 FM(QSPI0_IO2) FM(QSPI0_IO3) \
552 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
553 FM(QSPI1_IO2) FM(QSPI1_IO3) \
554 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
555 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
556 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
557 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
558 FM(PRESETOUT) \
559 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
560 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
561
562enum {
563 PINMUX_RESERVED = 0,
564
565 PINMUX_DATA_BEGIN,
566 GP_ALL(DATA),
567 PINMUX_DATA_END,
568
569#define F_(x, y)
570#define FM(x) FN_##x,
571 PINMUX_FUNCTION_BEGIN,
572 GP_ALL(FN),
573 PINMUX_GPSR
574 PINMUX_IPSR
575 PINMUX_MOD_SELS
576 PINMUX_FUNCTION_END,
577#undef F_
578#undef FM
579
580#define F_(x, y)
581#define FM(x) x##_MARK,
582 PINMUX_MARK_BEGIN,
583 PINMUX_GPSR
584 PINMUX_IPSR
585 PINMUX_MOD_SELS
586 PINMUX_STATIC
587 PINMUX_MARK_END,
588#undef F_
589#undef FM
590};
591
592static const u16 pinmux_data[] = {
593 PINMUX_DATA_GP_ALL(),
594
595 PINMUX_SINGLE(AVS1),
596 PINMUX_SINGLE(AVS2),
597 PINMUX_SINGLE(CLKOUT),
598 PINMUX_SINGLE(GP7_03),
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]599 PINMUX_SINGLE(GP7_02),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]600 PINMUX_SINGLE(MSIOF0_RXD),
601 PINMUX_SINGLE(MSIOF0_SCK),
602 PINMUX_SINGLE(MSIOF0_TXD),
603 PINMUX_SINGLE(SSI_SCK5),
604 PINMUX_SINGLE(SSI_SDATA5),
605 PINMUX_SINGLE(SSI_WS5),
606
607 /* IPSR0 */
608 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
609 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
610
611 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
612 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
613 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
614
615 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
616 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
617 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
618
619 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
620 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
621 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
622
623 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
626
627 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
628 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]629 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]630
631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
633 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
634 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
637 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
638
639 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
640 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
641 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
646
647 /* IPSR1 */
648 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
649 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
650 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
651 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
653 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
654
655 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
656 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]657 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
658 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
660 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
661
662 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
663 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
668
669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]671 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
672 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
673 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
685
686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_GPSR(IP1_31_28, A0),
691 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
692 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
693 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
694 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
695 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
696
697 /* IPSR2 */
698 PINMUX_IPSR_GPSR(IP2_3_0, A1),
699 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
700 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
701 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
702 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
703 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
704
705 PINMUX_IPSR_GPSR(IP2_7_4, A2),
706 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
707 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
709 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
710 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
711
712 PINMUX_IPSR_GPSR(IP2_11_8, A3),
713 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
714 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
715 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
716 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
717 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
718
719 PINMUX_IPSR_GPSR(IP2_15_12, A4),
720 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
721 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
724 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
725
726 PINMUX_IPSR_GPSR(IP2_19_16, A5),
727 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
728 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
729 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
732 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
733
734 PINMUX_IPSR_GPSR(IP2_23_20, A6),
735 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
736 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
740 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
741
742 PINMUX_IPSR_GPSR(IP2_27_24, A7),
743 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
744 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
745 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
748 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
749
750 PINMUX_IPSR_GPSR(IP2_31_28, A8),
751 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
755 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
756 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
757
758 /* IPSR3 */
759 PINMUX_IPSR_GPSR(IP3_3_0, A9),
760 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
762 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
763
764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
768
769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
770 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
771 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
774 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
775 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
776 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
778
779 PINMUX_IPSR_GPSR(IP3_15_12, A12),
780 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
781 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
782 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
783 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
784 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
785
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
787 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
788 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
789 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
790 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
791 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
792
793 PINMUX_IPSR_GPSR(IP3_23_20, A14),
794 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
795 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
796 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
797 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
798 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
799
800 PINMUX_IPSR_GPSR(IP3_27_24, A15),
801 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
802 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
804 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
805 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
806
807 PINMUX_IPSR_GPSR(IP3_31_28, A16),
808 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
809 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
810 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
811
812 /* IPSR4 */
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
814 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
815 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
816 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
817
818 PINMUX_IPSR_GPSR(IP4_7_4, A18),
819 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
820 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
822
823 PINMUX_IPSR_GPSR(IP4_11_8, A19),
824 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
825 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
826 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
827
828 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
829 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
830
831 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
832 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
833 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
834
835 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
836 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
837 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
838 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
840 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
841 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
842 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
843
844 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
845 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
846 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
850
851 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
852 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
853 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
857
858 /* IPSR5 */
859 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
860 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
861 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
862 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
864 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
865 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
873 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
874 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
875
876 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
877 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
879 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
880
881 PINMUX_IPSR_GPSR(IP5_15_12, D0),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
883 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
885 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
886
887 PINMUX_IPSR_GPSR(IP5_19_16, D1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
891 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
892
893 PINMUX_IPSR_GPSR(IP5_23_20, D2),
894 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
896 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
897
898 PINMUX_IPSR_GPSR(IP5_27_24, D3),
899 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
901 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
902
903 PINMUX_IPSR_GPSR(IP5_31_28, D4),
904 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
906 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
907
908 /* IPSR6 */
909 PINMUX_IPSR_GPSR(IP6_3_0, D5),
910 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
912 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
913
914 PINMUX_IPSR_GPSR(IP6_7_4, D6),
915 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
917 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
918
919 PINMUX_IPSR_GPSR(IP6_11_8, D7),
920 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
922 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
923
924 PINMUX_IPSR_GPSR(IP6_15_12, D8),
925 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
926 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
928 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
929 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
930
931 PINMUX_IPSR_GPSR(IP6_19_16, D9),
932 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
933 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
936
937 PINMUX_IPSR_GPSR(IP6_23_20, D10),
938 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
939 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
941 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
942 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
943 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
944
945 PINMUX_IPSR_GPSR(IP6_27_24, D11),
946 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
952
953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
954 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
955 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
956 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
957 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
958 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
959
960 /* IPSR7 */
961 PINMUX_IPSR_GPSR(IP7_3_0, D13),
962 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
963 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
967
968 PINMUX_IPSR_GPSR(IP7_7_4, D14),
969 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
970 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
971 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
972 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
974 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
975
976 PINMUX_IPSR_GPSR(IP7_11_8, D15),
977 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
978 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
979 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
980 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
982 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
983
984 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
985 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
986 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
987
988 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
989 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
990 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
991
992 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
993 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
995 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
996
997 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
998 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1001
1002 /* IPSR8 */
1003 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1004 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1009 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1012
1013 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1014 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1016
1017 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1018 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1019 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1020 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1021 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1022
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1024 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1025 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1026 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1027 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1028 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1029
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1031 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1032 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1033 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1034 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1036
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1038 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1039 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1040 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1041 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1043
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1045 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1046 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1047 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1048 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050
1051 /* IPSR9 */
1052 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1053 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1054
1055 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1056 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1057
1058 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1059 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1060
1061 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1062 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1063
1064 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1065 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1066
1067 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1068 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1069
1070 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1071 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1072
1073 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1074 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1075
1076 /* IPSR10 */
1077 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1078 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1079
1080 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1081 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1082
1083 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1084 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1085
1086 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1087 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1088
1089 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1090 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1091
1092 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1093 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1094 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1095
1096 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1097 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1099
1100 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1102 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1103
1104 /* IPSR11 */
1105 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1107 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1108
1109 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1110 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1111
1112 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1113 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1114 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1116
1117 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1118 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1119 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1120
1121 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1122 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1123 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1126 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDF_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1127 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1145
1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1206
1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1266
1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Hiroyuki Yokoyama8c7d64f2019-02-13 10:22:26 +0900[diff] [blame^]1270 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1307
1308 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1310
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1313
1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1354
1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1358
1359 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1360 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1361
1362 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1363 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1364
1365 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1366 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1367 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1368 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1369 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1370 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1372
1373 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1374 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1375 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1376 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1377 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1378 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1380
1381 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1382 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1383 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1384 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1385 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1386 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1389
1390 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1391 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1392 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1393 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1395 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1396 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1397
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1398 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1399 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1400 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1402 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1403 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1404 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1406
1407 /* IPSR17 */
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]1408 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1409
Hiroyuki Yokoyama46635762019-02-12 20:50:01 +0900[diff] [blame]1410 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1411 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1412 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1413 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1414 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1415
1416 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1417 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1418 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1419 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1420 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1421 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1422 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1423
1424 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1425 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1429 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1430
1431 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1432 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1433 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1434 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1435 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1436 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1437 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1438 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1439 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1440
1441 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1442 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1443 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1444 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1445 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1446 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1447 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1448 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1449 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1450
1451 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1452 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1453 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1454 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1455 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1456 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1457 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1459 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1460 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1461 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1462
1463 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1464 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1465 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1466 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1467 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1468 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1469 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1470 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1471 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1472
1473 /* IPSR18 */
1474 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1475 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1476 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1477 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1478 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1479 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1480 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1481 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1482 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1483
1484 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1485 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1486 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1487 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1488 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1489 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1490 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1491 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1492 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1493
1494 /* I2C */
1495 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1496 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1497 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1498
1499/*
1500 * Static pins can not be muxed between different functions but
1501 * still needs a mark entry in the pinmux list. Add each static
1502 * pin to the list without an associated function. The sh-pfc
1503 * core will do the right thing and skip trying to mux then pin
1504 * while still applying configuration to it
1505 */
1506#define FM(x) PINMUX_DATA(x##_MARK, 0),
1507 PINMUX_STATIC
1508#undef FM
1509};
1510
1511/*
1512 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1513 * Physical layout rows: A - AW, cols: 1 - 39.
1514 */
1515#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1516#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1517#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1518#define PIN_NONE U16_MAX
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1519
1520static const struct sh_pfc_pin pinmux_pins[] = {
1521 PINMUX_GPIO_GP_ALL(),
1522
1523 /*
1524 * Pins not associated with a GPIO port.
1525 *
1526 * The pin positions are different between different r8a7796
1527 * packages, all that is needed for the pfc driver is a unique
1528 * number for each pin. To this end use the pin layout from
1529 * R-Car M3SiP to calculate a unique number for each pin.
1530 */
1531 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1573};
1574
1575/* - AUDIO CLOCK ------------------------------------------------------------ */
1576static const unsigned int audio_clk_a_a_pins[] = {
1577 /* CLK A */
1578 RCAR_GP_PIN(6, 22),
1579};
1580static const unsigned int audio_clk_a_a_mux[] = {
1581 AUDIO_CLKA_A_MARK,
1582};
1583static const unsigned int audio_clk_a_b_pins[] = {
1584 /* CLK A */
1585 RCAR_GP_PIN(5, 4),
1586};
1587static const unsigned int audio_clk_a_b_mux[] = {
1588 AUDIO_CLKA_B_MARK,
1589};
1590static const unsigned int audio_clk_a_c_pins[] = {
1591 /* CLK A */
1592 RCAR_GP_PIN(5, 19),
1593};
1594static const unsigned int audio_clk_a_c_mux[] = {
1595 AUDIO_CLKA_C_MARK,
1596};
1597static const unsigned int audio_clk_b_a_pins[] = {
1598 /* CLK B */
1599 RCAR_GP_PIN(5, 12),
1600};
1601static const unsigned int audio_clk_b_a_mux[] = {
1602 AUDIO_CLKB_A_MARK,
1603};
1604static const unsigned int audio_clk_b_b_pins[] = {
1605 /* CLK B */
1606 RCAR_GP_PIN(6, 23),
1607};
1608static const unsigned int audio_clk_b_b_mux[] = {
1609 AUDIO_CLKB_B_MARK,
1610};
1611static const unsigned int audio_clk_c_a_pins[] = {
1612 /* CLK C */
1613 RCAR_GP_PIN(5, 21),
1614};
1615static const unsigned int audio_clk_c_a_mux[] = {
1616 AUDIO_CLKC_A_MARK,
1617};
1618static const unsigned int audio_clk_c_b_pins[] = {
1619 /* CLK C */
1620 RCAR_GP_PIN(5, 0),
1621};
1622static const unsigned int audio_clk_c_b_mux[] = {
1623 AUDIO_CLKC_B_MARK,
1624};
1625static const unsigned int audio_clkout_a_pins[] = {
1626 /* CLKOUT */
1627 RCAR_GP_PIN(5, 18),
1628};
1629static const unsigned int audio_clkout_a_mux[] = {
1630 AUDIO_CLKOUT_A_MARK,
1631};
1632static const unsigned int audio_clkout_b_pins[] = {
1633 /* CLKOUT */
1634 RCAR_GP_PIN(6, 28),
1635};
1636static const unsigned int audio_clkout_b_mux[] = {
1637 AUDIO_CLKOUT_B_MARK,
1638};
1639static const unsigned int audio_clkout_c_pins[] = {
1640 /* CLKOUT */
1641 RCAR_GP_PIN(5, 3),
1642};
1643static const unsigned int audio_clkout_c_mux[] = {
1644 AUDIO_CLKOUT_C_MARK,
1645};
1646static const unsigned int audio_clkout_d_pins[] = {
1647 /* CLKOUT */
1648 RCAR_GP_PIN(5, 21),
1649};
1650static const unsigned int audio_clkout_d_mux[] = {
1651 AUDIO_CLKOUT_D_MARK,
1652};
1653static const unsigned int audio_clkout1_a_pins[] = {
1654 /* CLKOUT1 */
1655 RCAR_GP_PIN(5, 15),
1656};
1657static const unsigned int audio_clkout1_a_mux[] = {
1658 AUDIO_CLKOUT1_A_MARK,
1659};
1660static const unsigned int audio_clkout1_b_pins[] = {
1661 /* CLKOUT1 */
1662 RCAR_GP_PIN(6, 29),
1663};
1664static const unsigned int audio_clkout1_b_mux[] = {
1665 AUDIO_CLKOUT1_B_MARK,
1666};
1667static const unsigned int audio_clkout2_a_pins[] = {
1668 /* CLKOUT2 */
1669 RCAR_GP_PIN(5, 16),
1670};
1671static const unsigned int audio_clkout2_a_mux[] = {
1672 AUDIO_CLKOUT2_A_MARK,
1673};
1674static const unsigned int audio_clkout2_b_pins[] = {
1675 /* CLKOUT2 */
1676 RCAR_GP_PIN(6, 30),
1677};
1678static const unsigned int audio_clkout2_b_mux[] = {
1679 AUDIO_CLKOUT2_B_MARK,
1680};
1681
1682static const unsigned int audio_clkout3_a_pins[] = {
1683 /* CLKOUT3 */
1684 RCAR_GP_PIN(5, 19),
1685};
1686static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688};
1689static const unsigned int audio_clkout3_b_pins[] = {
1690 /* CLKOUT3 */
1691 RCAR_GP_PIN(6, 31),
1692};
1693static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695};
1696
1697/* - EtherAVB --------------------------------------------------------------- */
1698static const unsigned int avb_link_pins[] = {
1699 /* AVB_LINK */
1700 RCAR_GP_PIN(2, 12),
1701};
1702static const unsigned int avb_link_mux[] = {
1703 AVB_LINK_MARK,
1704};
1705static const unsigned int avb_magic_pins[] = {
1706 /* AVB_MAGIC_ */
1707 RCAR_GP_PIN(2, 10),
1708};
1709static const unsigned int avb_magic_mux[] = {
1710 AVB_MAGIC_MARK,
1711};
1712static const unsigned int avb_phy_int_pins[] = {
1713 /* AVB_PHY_INT */
1714 RCAR_GP_PIN(2, 11),
1715};
1716static const unsigned int avb_phy_int_mux[] = {
1717 AVB_PHY_INT_MARK,
1718};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1719static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1720 /* AVB_MDC, AVB_MDIO */
1721 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1722};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1723static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1724 AVB_MDC_MARK, AVB_MDIO_MARK,
1725};
1726static const unsigned int avb_mii_pins[] = {
1727 /*
1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1729 * AVB_TD1, AVB_TD2, AVB_TD3,
1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1731 * AVB_RD1, AVB_RD2, AVB_RD3,
1732 * AVB_TXCREFCLK
1733 */
1734 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1735 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1736 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1737 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1738 PIN_NUMBER('A', 12),
1739
1740};
1741static const unsigned int avb_mii_mux[] = {
1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1746 AVB_TXCREFCLK_MARK,
1747};
1748static const unsigned int avb_avtp_pps_pins[] = {
1749 /* AVB_AVTP_PPS */
1750 RCAR_GP_PIN(2, 6),
1751};
1752static const unsigned int avb_avtp_pps_mux[] = {
1753 AVB_AVTP_PPS_MARK,
1754};
1755static const unsigned int avb_avtp_match_a_pins[] = {
1756 /* AVB_AVTP_MATCH_A */
1757 RCAR_GP_PIN(2, 13),
1758};
1759static const unsigned int avb_avtp_match_a_mux[] = {
1760 AVB_AVTP_MATCH_A_MARK,
1761};
1762static const unsigned int avb_avtp_capture_a_pins[] = {
1763 /* AVB_AVTP_CAPTURE_A */
1764 RCAR_GP_PIN(2, 14),
1765};
1766static const unsigned int avb_avtp_capture_a_mux[] = {
1767 AVB_AVTP_CAPTURE_A_MARK,
1768};
1769static const unsigned int avb_avtp_match_b_pins[] = {
1770 /* AVB_AVTP_MATCH_B */
1771 RCAR_GP_PIN(1, 8),
1772};
1773static const unsigned int avb_avtp_match_b_mux[] = {
1774 AVB_AVTP_MATCH_B_MARK,
1775};
1776static const unsigned int avb_avtp_capture_b_pins[] = {
1777 /* AVB_AVTP_CAPTURE_B */
1778 RCAR_GP_PIN(1, 11),
1779};
1780static const unsigned int avb_avtp_capture_b_mux[] = {
1781 AVB_AVTP_CAPTURE_B_MARK,
1782};
1783
1784/* - CAN ------------------------------------------------------------------ */
1785static const unsigned int can0_data_a_pins[] = {
1786 /* TX, RX */
1787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1788};
1789static const unsigned int can0_data_a_mux[] = {
1790 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1791};
1792static const unsigned int can0_data_b_pins[] = {
1793 /* TX, RX */
1794 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1795};
1796static const unsigned int can0_data_b_mux[] = {
1797 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1798};
1799static const unsigned int can1_data_pins[] = {
1800 /* TX, RX */
1801 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1802};
1803static const unsigned int can1_data_mux[] = {
1804 CAN1_TX_MARK, CAN1_RX_MARK,
1805};
1806
1807/* - CAN Clock -------------------------------------------------------------- */
1808static const unsigned int can_clk_pins[] = {
1809 /* CLK */
1810 RCAR_GP_PIN(1, 25),
1811};
1812static const unsigned int can_clk_mux[] = {
1813 CAN_CLK_MARK,
1814};
1815
1816/* - CAN FD --------------------------------------------------------------- */
1817static const unsigned int canfd0_data_a_pins[] = {
1818 /* TX, RX */
1819 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1820};
1821static const unsigned int canfd0_data_a_mux[] = {
1822 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1823};
1824static const unsigned int canfd0_data_b_pins[] = {
1825 /* TX, RX */
1826 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1827};
1828static const unsigned int canfd0_data_b_mux[] = {
1829 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1830};
1831static const unsigned int canfd1_data_pins[] = {
1832 /* TX, RX */
1833 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1834};
1835static const unsigned int canfd1_data_mux[] = {
1836 CANFD1_TX_MARK, CANFD1_RX_MARK,
1837};
1838
1839/* - DRIF0 --------------------------------------------------------------- */
1840static const unsigned int drif0_ctrl_a_pins[] = {
1841 /* CLK, SYNC */
1842 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1843};
1844static const unsigned int drif0_ctrl_a_mux[] = {
1845 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1846};
1847static const unsigned int drif0_data0_a_pins[] = {
1848 /* D0 */
1849 RCAR_GP_PIN(6, 10),
1850};
1851static const unsigned int drif0_data0_a_mux[] = {
1852 RIF0_D0_A_MARK,
1853};
1854static const unsigned int drif0_data1_a_pins[] = {
1855 /* D1 */
1856 RCAR_GP_PIN(6, 7),
1857};
1858static const unsigned int drif0_data1_a_mux[] = {
1859 RIF0_D1_A_MARK,
1860};
1861static const unsigned int drif0_ctrl_b_pins[] = {
1862 /* CLK, SYNC */
1863 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1864};
1865static const unsigned int drif0_ctrl_b_mux[] = {
1866 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1867};
1868static const unsigned int drif0_data0_b_pins[] = {
1869 /* D0 */
1870 RCAR_GP_PIN(5, 1),
1871};
1872static const unsigned int drif0_data0_b_mux[] = {
1873 RIF0_D0_B_MARK,
1874};
1875static const unsigned int drif0_data1_b_pins[] = {
1876 /* D1 */
1877 RCAR_GP_PIN(5, 2),
1878};
1879static const unsigned int drif0_data1_b_mux[] = {
1880 RIF0_D1_B_MARK,
1881};
1882static const unsigned int drif0_ctrl_c_pins[] = {
1883 /* CLK, SYNC */
1884 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1885};
1886static const unsigned int drif0_ctrl_c_mux[] = {
1887 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1888};
1889static const unsigned int drif0_data0_c_pins[] = {
1890 /* D0 */
1891 RCAR_GP_PIN(5, 13),
1892};
1893static const unsigned int drif0_data0_c_mux[] = {
1894 RIF0_D0_C_MARK,
1895};
1896static const unsigned int drif0_data1_c_pins[] = {
1897 /* D1 */
1898 RCAR_GP_PIN(5, 14),
1899};
1900static const unsigned int drif0_data1_c_mux[] = {
1901 RIF0_D1_C_MARK,
1902};
1903/* - DRIF1 --------------------------------------------------------------- */
1904static const unsigned int drif1_ctrl_a_pins[] = {
1905 /* CLK, SYNC */
1906 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1907};
1908static const unsigned int drif1_ctrl_a_mux[] = {
1909 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1910};
1911static const unsigned int drif1_data0_a_pins[] = {
1912 /* D0 */
1913 RCAR_GP_PIN(6, 19),
1914};
1915static const unsigned int drif1_data0_a_mux[] = {
1916 RIF1_D0_A_MARK,
1917};
1918static const unsigned int drif1_data1_a_pins[] = {
1919 /* D1 */
1920 RCAR_GP_PIN(6, 20),
1921};
1922static const unsigned int drif1_data1_a_mux[] = {
1923 RIF1_D1_A_MARK,
1924};
1925static const unsigned int drif1_ctrl_b_pins[] = {
1926 /* CLK, SYNC */
1927 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1928};
1929static const unsigned int drif1_ctrl_b_mux[] = {
1930 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1931};
1932static const unsigned int drif1_data0_b_pins[] = {
1933 /* D0 */
1934 RCAR_GP_PIN(5, 7),
1935};
1936static const unsigned int drif1_data0_b_mux[] = {
1937 RIF1_D0_B_MARK,
1938};
1939static const unsigned int drif1_data1_b_pins[] = {
1940 /* D1 */
1941 RCAR_GP_PIN(5, 8),
1942};
1943static const unsigned int drif1_data1_b_mux[] = {
1944 RIF1_D1_B_MARK,
1945};
1946static const unsigned int drif1_ctrl_c_pins[] = {
1947 /* CLK, SYNC */
1948 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1949};
1950static const unsigned int drif1_ctrl_c_mux[] = {
1951 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1952};
1953static const unsigned int drif1_data0_c_pins[] = {
1954 /* D0 */
1955 RCAR_GP_PIN(5, 6),
1956};
1957static const unsigned int drif1_data0_c_mux[] = {
1958 RIF1_D0_C_MARK,
1959};
1960static const unsigned int drif1_data1_c_pins[] = {
1961 /* D1 */
1962 RCAR_GP_PIN(5, 10),
1963};
1964static const unsigned int drif1_data1_c_mux[] = {
1965 RIF1_D1_C_MARK,
1966};
1967/* - DRIF2 --------------------------------------------------------------- */
1968static const unsigned int drif2_ctrl_a_pins[] = {
1969 /* CLK, SYNC */
1970 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1971};
1972static const unsigned int drif2_ctrl_a_mux[] = {
1973 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1974};
1975static const unsigned int drif2_data0_a_pins[] = {
1976 /* D0 */
1977 RCAR_GP_PIN(6, 7),
1978};
1979static const unsigned int drif2_data0_a_mux[] = {
1980 RIF2_D0_A_MARK,
1981};
1982static const unsigned int drif2_data1_a_pins[] = {
1983 /* D1 */
1984 RCAR_GP_PIN(6, 10),
1985};
1986static const unsigned int drif2_data1_a_mux[] = {
1987 RIF2_D1_A_MARK,
1988};
1989static const unsigned int drif2_ctrl_b_pins[] = {
1990 /* CLK, SYNC */
1991 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1992};
1993static const unsigned int drif2_ctrl_b_mux[] = {
1994 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1995};
1996static const unsigned int drif2_data0_b_pins[] = {
1997 /* D0 */
1998 RCAR_GP_PIN(6, 30),
1999};
2000static const unsigned int drif2_data0_b_mux[] = {
2001 RIF2_D0_B_MARK,
2002};
2003static const unsigned int drif2_data1_b_pins[] = {
2004 /* D1 */
2005 RCAR_GP_PIN(6, 31),
2006};
2007static const unsigned int drif2_data1_b_mux[] = {
2008 RIF2_D1_B_MARK,
2009};
2010/* - DRIF3 --------------------------------------------------------------- */
2011static const unsigned int drif3_ctrl_a_pins[] = {
2012 /* CLK, SYNC */
2013 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2014};
2015static const unsigned int drif3_ctrl_a_mux[] = {
2016 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2017};
2018static const unsigned int drif3_data0_a_pins[] = {
2019 /* D0 */
2020 RCAR_GP_PIN(6, 19),
2021};
2022static const unsigned int drif3_data0_a_mux[] = {
2023 RIF3_D0_A_MARK,
2024};
2025static const unsigned int drif3_data1_a_pins[] = {
2026 /* D1 */
2027 RCAR_GP_PIN(6, 20),
2028};
2029static const unsigned int drif3_data1_a_mux[] = {
2030 RIF3_D1_A_MARK,
2031};
2032static const unsigned int drif3_ctrl_b_pins[] = {
2033 /* CLK, SYNC */
2034 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2035};
2036static const unsigned int drif3_ctrl_b_mux[] = {
2037 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2038};
2039static const unsigned int drif3_data0_b_pins[] = {
2040 /* D0 */
2041 RCAR_GP_PIN(6, 28),
2042};
2043static const unsigned int drif3_data0_b_mux[] = {
2044 RIF3_D0_B_MARK,
2045};
2046static const unsigned int drif3_data1_b_pins[] = {
2047 /* D1 */
2048 RCAR_GP_PIN(6, 29),
2049};
2050static const unsigned int drif3_data1_b_mux[] = {
2051 RIF3_D1_B_MARK,
2052};
2053
2054/* - DU --------------------------------------------------------------------- */
2055static const unsigned int du_rgb666_pins[] = {
2056 /* R[7:2], G[7:2], B[7:2] */
2057 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2058 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2059 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2060 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2061 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2062 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2063};
2064static const unsigned int du_rgb666_mux[] = {
2065 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2066 DU_DR3_MARK, DU_DR2_MARK,
2067 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2068 DU_DG3_MARK, DU_DG2_MARK,
2069 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2070 DU_DB3_MARK, DU_DB2_MARK,
2071};
2072static const unsigned int du_rgb888_pins[] = {
2073 /* R[7:0], G[7:0], B[7:0] */
2074 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2075 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2076 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2077 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2078 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2079 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2080 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2081 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2082 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2083};
2084static const unsigned int du_rgb888_mux[] = {
2085 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2086 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2087 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2088 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2089 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2090 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2091};
2092static const unsigned int du_clk_out_0_pins[] = {
2093 /* CLKOUT */
2094 RCAR_GP_PIN(1, 27),
2095};
2096static const unsigned int du_clk_out_0_mux[] = {
2097 DU_DOTCLKOUT0_MARK
2098};
2099static const unsigned int du_clk_out_1_pins[] = {
2100 /* CLKOUT */
2101 RCAR_GP_PIN(2, 3),
2102};
2103static const unsigned int du_clk_out_1_mux[] = {
2104 DU_DOTCLKOUT1_MARK
2105};
2106static const unsigned int du_sync_pins[] = {
2107 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2108 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2109};
2110static const unsigned int du_sync_mux[] = {
2111 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2112};
2113static const unsigned int du_oddf_pins[] = {
2114 /* EXDISP/EXODDF/EXCDE */
2115 RCAR_GP_PIN(2, 2),
2116};
2117static const unsigned int du_oddf_mux[] = {
2118 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2119};
2120static const unsigned int du_cde_pins[] = {
2121 /* CDE */
2122 RCAR_GP_PIN(2, 0),
2123};
2124static const unsigned int du_cde_mux[] = {
2125 DU_CDE_MARK,
2126};
2127static const unsigned int du_disp_pins[] = {
2128 /* DISP */
2129 RCAR_GP_PIN(2, 1),
2130};
2131static const unsigned int du_disp_mux[] = {
2132 DU_DISP_MARK,
2133};
2134
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]2135/* - GP7_02/03 -------------------------------------------------------------- */
2136static const unsigned int gp7_02_pins[] = {
2137 /* GP7_02 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2138 RCAR_GP_PIN(7, 2),
2139};
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]2140
2141static const unsigned int gp7_02_mux[] = {
2142 GP7_02_MARK,
2143};
2144
2145static const unsigned int gp7_03_pins[] = {
2146 /* GP7_03 */
2147 RCAR_GP_PIN(7, 3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2148};
2149
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]2150static const unsigned int gp7_03_mux[] = {
2151 GP7_03_MARK,
2152};
2153
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2154/* - HSCIF0 ----------------------------------------------------------------- */
2155static const unsigned int hscif0_data_pins[] = {
2156 /* RX, TX */
2157 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2158};
2159static const unsigned int hscif0_data_mux[] = {
2160 HRX0_MARK, HTX0_MARK,
2161};
2162static const unsigned int hscif0_clk_pins[] = {
2163 /* SCK */
2164 RCAR_GP_PIN(5, 12),
2165};
2166static const unsigned int hscif0_clk_mux[] = {
2167 HSCK0_MARK,
2168};
2169static const unsigned int hscif0_ctrl_pins[] = {
2170 /* RTS, CTS */
2171 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2172};
2173static const unsigned int hscif0_ctrl_mux[] = {
2174 HRTS0_N_MARK, HCTS0_N_MARK,
2175};
2176/* - HSCIF1 ----------------------------------------------------------------- */
2177static const unsigned int hscif1_data_a_pins[] = {
2178 /* RX, TX */
2179 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2180};
2181static const unsigned int hscif1_data_a_mux[] = {
2182 HRX1_A_MARK, HTX1_A_MARK,
2183};
2184static const unsigned int hscif1_clk_a_pins[] = {
2185 /* SCK */
2186 RCAR_GP_PIN(6, 21),
2187};
2188static const unsigned int hscif1_clk_a_mux[] = {
2189 HSCK1_A_MARK,
2190};
2191static const unsigned int hscif1_ctrl_a_pins[] = {
2192 /* RTS, CTS */
2193 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2194};
2195static const unsigned int hscif1_ctrl_a_mux[] = {
2196 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2197};
2198
2199static const unsigned int hscif1_data_b_pins[] = {
2200 /* RX, TX */
2201 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2202};
2203static const unsigned int hscif1_data_b_mux[] = {
2204 HRX1_B_MARK, HTX1_B_MARK,
2205};
2206static const unsigned int hscif1_clk_b_pins[] = {
2207 /* SCK */
2208 RCAR_GP_PIN(5, 0),
2209};
2210static const unsigned int hscif1_clk_b_mux[] = {
2211 HSCK1_B_MARK,
2212};
2213static const unsigned int hscif1_ctrl_b_pins[] = {
2214 /* RTS, CTS */
2215 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2216};
2217static const unsigned int hscif1_ctrl_b_mux[] = {
2218 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2219};
2220/* - HSCIF2 ----------------------------------------------------------------- */
2221static const unsigned int hscif2_data_a_pins[] = {
2222 /* RX, TX */
2223 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2224};
2225static const unsigned int hscif2_data_a_mux[] = {
2226 HRX2_A_MARK, HTX2_A_MARK,
2227};
2228static const unsigned int hscif2_clk_a_pins[] = {
2229 /* SCK */
2230 RCAR_GP_PIN(6, 10),
2231};
2232static const unsigned int hscif2_clk_a_mux[] = {
2233 HSCK2_A_MARK,
2234};
2235static const unsigned int hscif2_ctrl_a_pins[] = {
2236 /* RTS, CTS */
2237 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2238};
2239static const unsigned int hscif2_ctrl_a_mux[] = {
2240 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2241};
2242
2243static const unsigned int hscif2_data_b_pins[] = {
2244 /* RX, TX */
2245 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2246};
2247static const unsigned int hscif2_data_b_mux[] = {
2248 HRX2_B_MARK, HTX2_B_MARK,
2249};
2250static const unsigned int hscif2_clk_b_pins[] = {
2251 /* SCK */
2252 RCAR_GP_PIN(6, 21),
2253};
2254static const unsigned int hscif2_clk_b_mux[] = {
2255 HSCK2_B_MARK,
2256};
2257static const unsigned int hscif2_ctrl_b_pins[] = {
2258 /* RTS, CTS */
2259 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2260};
2261static const unsigned int hscif2_ctrl_b_mux[] = {
2262 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2263};
2264
2265static const unsigned int hscif2_data_c_pins[] = {
2266 /* RX, TX */
2267 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2268};
2269static const unsigned int hscif2_data_c_mux[] = {
2270 HRX2_C_MARK, HTX2_C_MARK,
2271};
2272static const unsigned int hscif2_clk_c_pins[] = {
2273 /* SCK */
2274 RCAR_GP_PIN(6, 24),
2275};
2276static const unsigned int hscif2_clk_c_mux[] = {
2277 HSCK2_C_MARK,
2278};
2279static const unsigned int hscif2_ctrl_c_pins[] = {
2280 /* RTS, CTS */
2281 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2282};
2283static const unsigned int hscif2_ctrl_c_mux[] = {
2284 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2285};
2286/* - HSCIF3 ----------------------------------------------------------------- */
2287static const unsigned int hscif3_data_a_pins[] = {
2288 /* RX, TX */
2289 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2290};
2291static const unsigned int hscif3_data_a_mux[] = {
2292 HRX3_A_MARK, HTX3_A_MARK,
2293};
2294static const unsigned int hscif3_clk_pins[] = {
2295 /* SCK */
2296 RCAR_GP_PIN(1, 22),
2297};
2298static const unsigned int hscif3_clk_mux[] = {
2299 HSCK3_MARK,
2300};
2301static const unsigned int hscif3_ctrl_pins[] = {
2302 /* RTS, CTS */
2303 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2304};
2305static const unsigned int hscif3_ctrl_mux[] = {
2306 HRTS3_N_MARK, HCTS3_N_MARK,
2307};
2308
2309static const unsigned int hscif3_data_b_pins[] = {
2310 /* RX, TX */
2311 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2312};
2313static const unsigned int hscif3_data_b_mux[] = {
2314 HRX3_B_MARK, HTX3_B_MARK,
2315};
2316static const unsigned int hscif3_data_c_pins[] = {
2317 /* RX, TX */
2318 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2319};
2320static const unsigned int hscif3_data_c_mux[] = {
2321 HRX3_C_MARK, HTX3_C_MARK,
2322};
2323static const unsigned int hscif3_data_d_pins[] = {
2324 /* RX, TX */
2325 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2326};
2327static const unsigned int hscif3_data_d_mux[] = {
2328 HRX3_D_MARK, HTX3_D_MARK,
2329};
2330/* - HSCIF4 ----------------------------------------------------------------- */
2331static const unsigned int hscif4_data_a_pins[] = {
2332 /* RX, TX */
2333 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2334};
2335static const unsigned int hscif4_data_a_mux[] = {
2336 HRX4_A_MARK, HTX4_A_MARK,
2337};
2338static const unsigned int hscif4_clk_pins[] = {
2339 /* SCK */
2340 RCAR_GP_PIN(1, 11),
2341};
2342static const unsigned int hscif4_clk_mux[] = {
2343 HSCK4_MARK,
2344};
2345static const unsigned int hscif4_ctrl_pins[] = {
2346 /* RTS, CTS */
2347 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2348};
2349static const unsigned int hscif4_ctrl_mux[] = {
2350 HRTS4_N_MARK, HCTS4_N_MARK,
2351};
2352
2353static const unsigned int hscif4_data_b_pins[] = {
2354 /* RX, TX */
2355 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2356};
2357static const unsigned int hscif4_data_b_mux[] = {
2358 HRX4_B_MARK, HTX4_B_MARK,
2359};
2360
2361/* - I2C -------------------------------------------------------------------- */
2362static const unsigned int i2c1_a_pins[] = {
2363 /* SDA, SCL */
2364 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2365};
2366static const unsigned int i2c1_a_mux[] = {
2367 SDA1_A_MARK, SCL1_A_MARK,
2368};
2369static const unsigned int i2c1_b_pins[] = {
2370 /* SDA, SCL */
2371 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2372};
2373static const unsigned int i2c1_b_mux[] = {
2374 SDA1_B_MARK, SCL1_B_MARK,
2375};
2376static const unsigned int i2c2_a_pins[] = {
2377 /* SDA, SCL */
2378 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2379};
2380static const unsigned int i2c2_a_mux[] = {
2381 SDA2_A_MARK, SCL2_A_MARK,
2382};
2383static const unsigned int i2c2_b_pins[] = {
2384 /* SDA, SCL */
2385 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2386};
2387static const unsigned int i2c2_b_mux[] = {
2388 SDA2_B_MARK, SCL2_B_MARK,
2389};
2390static const unsigned int i2c6_a_pins[] = {
2391 /* SDA, SCL */
2392 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2393};
2394static const unsigned int i2c6_a_mux[] = {
2395 SDA6_A_MARK, SCL6_A_MARK,
2396};
2397static const unsigned int i2c6_b_pins[] = {
2398 /* SDA, SCL */
2399 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2400};
2401static const unsigned int i2c6_b_mux[] = {
2402 SDA6_B_MARK, SCL6_B_MARK,
2403};
2404static const unsigned int i2c6_c_pins[] = {
2405 /* SDA, SCL */
2406 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2407};
2408static const unsigned int i2c6_c_mux[] = {
2409 SDA6_C_MARK, SCL6_C_MARK,
2410};
2411
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2412/* - INTC-EX ---------------------------------------------------------------- */
2413static const unsigned int intc_ex_irq0_pins[] = {
2414 /* IRQ0 */
2415 RCAR_GP_PIN(2, 0),
2416};
2417static const unsigned int intc_ex_irq0_mux[] = {
2418 IRQ0_MARK,
2419};
2420static const unsigned int intc_ex_irq1_pins[] = {
2421 /* IRQ1 */
2422 RCAR_GP_PIN(2, 1),
2423};
2424static const unsigned int intc_ex_irq1_mux[] = {
2425 IRQ1_MARK,
2426};
2427static const unsigned int intc_ex_irq2_pins[] = {
2428 /* IRQ2 */
2429 RCAR_GP_PIN(2, 2),
2430};
2431static const unsigned int intc_ex_irq2_mux[] = {
2432 IRQ2_MARK,
2433};
2434static const unsigned int intc_ex_irq3_pins[] = {
2435 /* IRQ3 */
2436 RCAR_GP_PIN(2, 3),
2437};
2438static const unsigned int intc_ex_irq3_mux[] = {
2439 IRQ3_MARK,
2440};
2441static const unsigned int intc_ex_irq4_pins[] = {
2442 /* IRQ4 */
2443 RCAR_GP_PIN(2, 4),
2444};
2445static const unsigned int intc_ex_irq4_mux[] = {
2446 IRQ4_MARK,
2447};
2448static const unsigned int intc_ex_irq5_pins[] = {
2449 /* IRQ5 */
2450 RCAR_GP_PIN(2, 5),
2451};
2452static const unsigned int intc_ex_irq5_mux[] = {
2453 IRQ5_MARK,
2454};
2455
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2456/* - MSIOF0 ----------------------------------------------------------------- */
2457static const unsigned int msiof0_clk_pins[] = {
2458 /* SCK */
2459 RCAR_GP_PIN(5, 17),
2460};
2461static const unsigned int msiof0_clk_mux[] = {
2462 MSIOF0_SCK_MARK,
2463};
2464static const unsigned int msiof0_sync_pins[] = {
2465 /* SYNC */
2466 RCAR_GP_PIN(5, 18),
2467};
2468static const unsigned int msiof0_sync_mux[] = {
2469 MSIOF0_SYNC_MARK,
2470};
2471static const unsigned int msiof0_ss1_pins[] = {
2472 /* SS1 */
2473 RCAR_GP_PIN(5, 19),
2474};
2475static const unsigned int msiof0_ss1_mux[] = {
2476 MSIOF0_SS1_MARK,
2477};
2478static const unsigned int msiof0_ss2_pins[] = {
2479 /* SS2 */
2480 RCAR_GP_PIN(5, 21),
2481};
2482static const unsigned int msiof0_ss2_mux[] = {
2483 MSIOF0_SS2_MARK,
2484};
2485static const unsigned int msiof0_txd_pins[] = {
2486 /* TXD */
2487 RCAR_GP_PIN(5, 20),
2488};
2489static const unsigned int msiof0_txd_mux[] = {
2490 MSIOF0_TXD_MARK,
2491};
2492static const unsigned int msiof0_rxd_pins[] = {
2493 /* RXD */
2494 RCAR_GP_PIN(5, 22),
2495};
2496static const unsigned int msiof0_rxd_mux[] = {
2497 MSIOF0_RXD_MARK,
2498};
2499/* - MSIOF1 ----------------------------------------------------------------- */
2500static const unsigned int msiof1_clk_a_pins[] = {
2501 /* SCK */
2502 RCAR_GP_PIN(6, 8),
2503};
2504static const unsigned int msiof1_clk_a_mux[] = {
2505 MSIOF1_SCK_A_MARK,
2506};
2507static const unsigned int msiof1_sync_a_pins[] = {
2508 /* SYNC */
2509 RCAR_GP_PIN(6, 9),
2510};
2511static const unsigned int msiof1_sync_a_mux[] = {
2512 MSIOF1_SYNC_A_MARK,
2513};
2514static const unsigned int msiof1_ss1_a_pins[] = {
2515 /* SS1 */
2516 RCAR_GP_PIN(6, 5),
2517};
2518static const unsigned int msiof1_ss1_a_mux[] = {
2519 MSIOF1_SS1_A_MARK,
2520};
2521static const unsigned int msiof1_ss2_a_pins[] = {
2522 /* SS2 */
2523 RCAR_GP_PIN(6, 6),
2524};
2525static const unsigned int msiof1_ss2_a_mux[] = {
2526 MSIOF1_SS2_A_MARK,
2527};
2528static const unsigned int msiof1_txd_a_pins[] = {
2529 /* TXD */
2530 RCAR_GP_PIN(6, 7),
2531};
2532static const unsigned int msiof1_txd_a_mux[] = {
2533 MSIOF1_TXD_A_MARK,
2534};
2535static const unsigned int msiof1_rxd_a_pins[] = {
2536 /* RXD */
2537 RCAR_GP_PIN(6, 10),
2538};
2539static const unsigned int msiof1_rxd_a_mux[] = {
2540 MSIOF1_RXD_A_MARK,
2541};
2542static const unsigned int msiof1_clk_b_pins[] = {
2543 /* SCK */
2544 RCAR_GP_PIN(5, 9),
2545};
2546static const unsigned int msiof1_clk_b_mux[] = {
2547 MSIOF1_SCK_B_MARK,
2548};
2549static const unsigned int msiof1_sync_b_pins[] = {
2550 /* SYNC */
2551 RCAR_GP_PIN(5, 3),
2552};
2553static const unsigned int msiof1_sync_b_mux[] = {
2554 MSIOF1_SYNC_B_MARK,
2555};
2556static const unsigned int msiof1_ss1_b_pins[] = {
2557 /* SS1 */
2558 RCAR_GP_PIN(5, 4),
2559};
2560static const unsigned int msiof1_ss1_b_mux[] = {
2561 MSIOF1_SS1_B_MARK,
2562};
2563static const unsigned int msiof1_ss2_b_pins[] = {
2564 /* SS2 */
2565 RCAR_GP_PIN(5, 0),
2566};
2567static const unsigned int msiof1_ss2_b_mux[] = {
2568 MSIOF1_SS2_B_MARK,
2569};
2570static const unsigned int msiof1_txd_b_pins[] = {
2571 /* TXD */
2572 RCAR_GP_PIN(5, 8),
2573};
2574static const unsigned int msiof1_txd_b_mux[] = {
2575 MSIOF1_TXD_B_MARK,
2576};
2577static const unsigned int msiof1_rxd_b_pins[] = {
2578 /* RXD */
2579 RCAR_GP_PIN(5, 7),
2580};
2581static const unsigned int msiof1_rxd_b_mux[] = {
2582 MSIOF1_RXD_B_MARK,
2583};
2584static const unsigned int msiof1_clk_c_pins[] = {
2585 /* SCK */
2586 RCAR_GP_PIN(6, 17),
2587};
2588static const unsigned int msiof1_clk_c_mux[] = {
2589 MSIOF1_SCK_C_MARK,
2590};
2591static const unsigned int msiof1_sync_c_pins[] = {
2592 /* SYNC */
2593 RCAR_GP_PIN(6, 18),
2594};
2595static const unsigned int msiof1_sync_c_mux[] = {
2596 MSIOF1_SYNC_C_MARK,
2597};
2598static const unsigned int msiof1_ss1_c_pins[] = {
2599 /* SS1 */
2600 RCAR_GP_PIN(6, 21),
2601};
2602static const unsigned int msiof1_ss1_c_mux[] = {
2603 MSIOF1_SS1_C_MARK,
2604};
2605static const unsigned int msiof1_ss2_c_pins[] = {
2606 /* SS2 */
2607 RCAR_GP_PIN(6, 27),
2608};
2609static const unsigned int msiof1_ss2_c_mux[] = {
2610 MSIOF1_SS2_C_MARK,
2611};
2612static const unsigned int msiof1_txd_c_pins[] = {
2613 /* TXD */
2614 RCAR_GP_PIN(6, 20),
2615};
2616static const unsigned int msiof1_txd_c_mux[] = {
2617 MSIOF1_TXD_C_MARK,
2618};
2619static const unsigned int msiof1_rxd_c_pins[] = {
2620 /* RXD */
2621 RCAR_GP_PIN(6, 19),
2622};
2623static const unsigned int msiof1_rxd_c_mux[] = {
2624 MSIOF1_RXD_C_MARK,
2625};
2626static const unsigned int msiof1_clk_d_pins[] = {
2627 /* SCK */
2628 RCAR_GP_PIN(5, 12),
2629};
2630static const unsigned int msiof1_clk_d_mux[] = {
2631 MSIOF1_SCK_D_MARK,
2632};
2633static const unsigned int msiof1_sync_d_pins[] = {
2634 /* SYNC */
2635 RCAR_GP_PIN(5, 15),
2636};
2637static const unsigned int msiof1_sync_d_mux[] = {
2638 MSIOF1_SYNC_D_MARK,
2639};
2640static const unsigned int msiof1_ss1_d_pins[] = {
2641 /* SS1 */
2642 RCAR_GP_PIN(5, 16),
2643};
2644static const unsigned int msiof1_ss1_d_mux[] = {
2645 MSIOF1_SS1_D_MARK,
2646};
2647static const unsigned int msiof1_ss2_d_pins[] = {
2648 /* SS2 */
2649 RCAR_GP_PIN(5, 21),
2650};
2651static const unsigned int msiof1_ss2_d_mux[] = {
2652 MSIOF1_SS2_D_MARK,
2653};
2654static const unsigned int msiof1_txd_d_pins[] = {
2655 /* TXD */
2656 RCAR_GP_PIN(5, 14),
2657};
2658static const unsigned int msiof1_txd_d_mux[] = {
2659 MSIOF1_TXD_D_MARK,
2660};
2661static const unsigned int msiof1_rxd_d_pins[] = {
2662 /* RXD */
2663 RCAR_GP_PIN(5, 13),
2664};
2665static const unsigned int msiof1_rxd_d_mux[] = {
2666 MSIOF1_RXD_D_MARK,
2667};
2668static const unsigned int msiof1_clk_e_pins[] = {
2669 /* SCK */
2670 RCAR_GP_PIN(3, 0),
2671};
2672static const unsigned int msiof1_clk_e_mux[] = {
2673 MSIOF1_SCK_E_MARK,
2674};
2675static const unsigned int msiof1_sync_e_pins[] = {
2676 /* SYNC */
2677 RCAR_GP_PIN(3, 1),
2678};
2679static const unsigned int msiof1_sync_e_mux[] = {
2680 MSIOF1_SYNC_E_MARK,
2681};
2682static const unsigned int msiof1_ss1_e_pins[] = {
2683 /* SS1 */
2684 RCAR_GP_PIN(3, 4),
2685};
2686static const unsigned int msiof1_ss1_e_mux[] = {
2687 MSIOF1_SS1_E_MARK,
2688};
2689static const unsigned int msiof1_ss2_e_pins[] = {
2690 /* SS2 */
2691 RCAR_GP_PIN(3, 5),
2692};
2693static const unsigned int msiof1_ss2_e_mux[] = {
2694 MSIOF1_SS2_E_MARK,
2695};
2696static const unsigned int msiof1_txd_e_pins[] = {
2697 /* TXD */
2698 RCAR_GP_PIN(3, 3),
2699};
2700static const unsigned int msiof1_txd_e_mux[] = {
2701 MSIOF1_TXD_E_MARK,
2702};
2703static const unsigned int msiof1_rxd_e_pins[] = {
2704 /* RXD */
2705 RCAR_GP_PIN(3, 2),
2706};
2707static const unsigned int msiof1_rxd_e_mux[] = {
2708 MSIOF1_RXD_E_MARK,
2709};
2710static const unsigned int msiof1_clk_f_pins[] = {
2711 /* SCK */
2712 RCAR_GP_PIN(5, 23),
2713};
2714static const unsigned int msiof1_clk_f_mux[] = {
2715 MSIOF1_SCK_F_MARK,
2716};
2717static const unsigned int msiof1_sync_f_pins[] = {
2718 /* SYNC */
2719 RCAR_GP_PIN(5, 24),
2720};
2721static const unsigned int msiof1_sync_f_mux[] = {
2722 MSIOF1_SYNC_F_MARK,
2723};
2724static const unsigned int msiof1_ss1_f_pins[] = {
2725 /* SS1 */
2726 RCAR_GP_PIN(6, 1),
2727};
2728static const unsigned int msiof1_ss1_f_mux[] = {
2729 MSIOF1_SS1_F_MARK,
2730};
2731static const unsigned int msiof1_ss2_f_pins[] = {
2732 /* SS2 */
2733 RCAR_GP_PIN(6, 2),
2734};
2735static const unsigned int msiof1_ss2_f_mux[] = {
2736 MSIOF1_SS2_F_MARK,
2737};
2738static const unsigned int msiof1_txd_f_pins[] = {
2739 /* TXD */
2740 RCAR_GP_PIN(6, 0),
2741};
2742static const unsigned int msiof1_txd_f_mux[] = {
2743 MSIOF1_TXD_F_MARK,
2744};
2745static const unsigned int msiof1_rxd_f_pins[] = {
2746 /* RXD */
2747 RCAR_GP_PIN(5, 25),
2748};
2749static const unsigned int msiof1_rxd_f_mux[] = {
2750 MSIOF1_RXD_F_MARK,
2751};
2752static const unsigned int msiof1_clk_g_pins[] = {
2753 /* SCK */
2754 RCAR_GP_PIN(3, 6),
2755};
2756static const unsigned int msiof1_clk_g_mux[] = {
2757 MSIOF1_SCK_G_MARK,
2758};
2759static const unsigned int msiof1_sync_g_pins[] = {
2760 /* SYNC */
2761 RCAR_GP_PIN(3, 7),
2762};
2763static const unsigned int msiof1_sync_g_mux[] = {
2764 MSIOF1_SYNC_G_MARK,
2765};
2766static const unsigned int msiof1_ss1_g_pins[] = {
2767 /* SS1 */
2768 RCAR_GP_PIN(3, 10),
2769};
2770static const unsigned int msiof1_ss1_g_mux[] = {
2771 MSIOF1_SS1_G_MARK,
2772};
2773static const unsigned int msiof1_ss2_g_pins[] = {
2774 /* SS2 */
2775 RCAR_GP_PIN(3, 11),
2776};
2777static const unsigned int msiof1_ss2_g_mux[] = {
2778 MSIOF1_SS2_G_MARK,
2779};
2780static const unsigned int msiof1_txd_g_pins[] = {
2781 /* TXD */
2782 RCAR_GP_PIN(3, 9),
2783};
2784static const unsigned int msiof1_txd_g_mux[] = {
2785 MSIOF1_TXD_G_MARK,
2786};
2787static const unsigned int msiof1_rxd_g_pins[] = {
2788 /* RXD */
2789 RCAR_GP_PIN(3, 8),
2790};
2791static const unsigned int msiof1_rxd_g_mux[] = {
2792 MSIOF1_RXD_G_MARK,
2793};
2794/* - MSIOF2 ----------------------------------------------------------------- */
2795static const unsigned int msiof2_clk_a_pins[] = {
2796 /* SCK */
2797 RCAR_GP_PIN(1, 9),
2798};
2799static const unsigned int msiof2_clk_a_mux[] = {
2800 MSIOF2_SCK_A_MARK,
2801};
2802static const unsigned int msiof2_sync_a_pins[] = {
2803 /* SYNC */
2804 RCAR_GP_PIN(1, 8),
2805};
2806static const unsigned int msiof2_sync_a_mux[] = {
2807 MSIOF2_SYNC_A_MARK,
2808};
2809static const unsigned int msiof2_ss1_a_pins[] = {
2810 /* SS1 */
2811 RCAR_GP_PIN(1, 6),
2812};
2813static const unsigned int msiof2_ss1_a_mux[] = {
2814 MSIOF2_SS1_A_MARK,
2815};
2816static const unsigned int msiof2_ss2_a_pins[] = {
2817 /* SS2 */
2818 RCAR_GP_PIN(1, 7),
2819};
2820static const unsigned int msiof2_ss2_a_mux[] = {
2821 MSIOF2_SS2_A_MARK,
2822};
2823static const unsigned int msiof2_txd_a_pins[] = {
2824 /* TXD */
2825 RCAR_GP_PIN(1, 11),
2826};
2827static const unsigned int msiof2_txd_a_mux[] = {
2828 MSIOF2_TXD_A_MARK,
2829};
2830static const unsigned int msiof2_rxd_a_pins[] = {
2831 /* RXD */
2832 RCAR_GP_PIN(1, 10),
2833};
2834static const unsigned int msiof2_rxd_a_mux[] = {
2835 MSIOF2_RXD_A_MARK,
2836};
2837static const unsigned int msiof2_clk_b_pins[] = {
2838 /* SCK */
2839 RCAR_GP_PIN(0, 4),
2840};
2841static const unsigned int msiof2_clk_b_mux[] = {
2842 MSIOF2_SCK_B_MARK,
2843};
2844static const unsigned int msiof2_sync_b_pins[] = {
2845 /* SYNC */
2846 RCAR_GP_PIN(0, 5),
2847};
2848static const unsigned int msiof2_sync_b_mux[] = {
2849 MSIOF2_SYNC_B_MARK,
2850};
2851static const unsigned int msiof2_ss1_b_pins[] = {
2852 /* SS1 */
2853 RCAR_GP_PIN(0, 0),
2854};
2855static const unsigned int msiof2_ss1_b_mux[] = {
2856 MSIOF2_SS1_B_MARK,
2857};
2858static const unsigned int msiof2_ss2_b_pins[] = {
2859 /* SS2 */
2860 RCAR_GP_PIN(0, 1),
2861};
2862static const unsigned int msiof2_ss2_b_mux[] = {
2863 MSIOF2_SS2_B_MARK,
2864};
2865static const unsigned int msiof2_txd_b_pins[] = {
2866 /* TXD */
2867 RCAR_GP_PIN(0, 7),
2868};
2869static const unsigned int msiof2_txd_b_mux[] = {
2870 MSIOF2_TXD_B_MARK,
2871};
2872static const unsigned int msiof2_rxd_b_pins[] = {
2873 /* RXD */
2874 RCAR_GP_PIN(0, 6),
2875};
2876static const unsigned int msiof2_rxd_b_mux[] = {
2877 MSIOF2_RXD_B_MARK,
2878};
2879static const unsigned int msiof2_clk_c_pins[] = {
2880 /* SCK */
2881 RCAR_GP_PIN(2, 12),
2882};
2883static const unsigned int msiof2_clk_c_mux[] = {
2884 MSIOF2_SCK_C_MARK,
2885};
2886static const unsigned int msiof2_sync_c_pins[] = {
2887 /* SYNC */
2888 RCAR_GP_PIN(2, 11),
2889};
2890static const unsigned int msiof2_sync_c_mux[] = {
2891 MSIOF2_SYNC_C_MARK,
2892};
2893static const unsigned int msiof2_ss1_c_pins[] = {
2894 /* SS1 */
2895 RCAR_GP_PIN(2, 10),
2896};
2897static const unsigned int msiof2_ss1_c_mux[] = {
2898 MSIOF2_SS1_C_MARK,
2899};
2900static const unsigned int msiof2_ss2_c_pins[] = {
2901 /* SS2 */
2902 RCAR_GP_PIN(2, 9),
2903};
2904static const unsigned int msiof2_ss2_c_mux[] = {
2905 MSIOF2_SS2_C_MARK,
2906};
2907static const unsigned int msiof2_txd_c_pins[] = {
2908 /* TXD */
2909 RCAR_GP_PIN(2, 14),
2910};
2911static const unsigned int msiof2_txd_c_mux[] = {
2912 MSIOF2_TXD_C_MARK,
2913};
2914static const unsigned int msiof2_rxd_c_pins[] = {
2915 /* RXD */
2916 RCAR_GP_PIN(2, 13),
2917};
2918static const unsigned int msiof2_rxd_c_mux[] = {
2919 MSIOF2_RXD_C_MARK,
2920};
2921static const unsigned int msiof2_clk_d_pins[] = {
2922 /* SCK */
2923 RCAR_GP_PIN(0, 8),
2924};
2925static const unsigned int msiof2_clk_d_mux[] = {
2926 MSIOF2_SCK_D_MARK,
2927};
2928static const unsigned int msiof2_sync_d_pins[] = {
2929 /* SYNC */
2930 RCAR_GP_PIN(0, 9),
2931};
2932static const unsigned int msiof2_sync_d_mux[] = {
2933 MSIOF2_SYNC_D_MARK,
2934};
2935static const unsigned int msiof2_ss1_d_pins[] = {
2936 /* SS1 */
2937 RCAR_GP_PIN(0, 12),
2938};
2939static const unsigned int msiof2_ss1_d_mux[] = {
2940 MSIOF2_SS1_D_MARK,
2941};
2942static const unsigned int msiof2_ss2_d_pins[] = {
2943 /* SS2 */
2944 RCAR_GP_PIN(0, 13),
2945};
2946static const unsigned int msiof2_ss2_d_mux[] = {
2947 MSIOF2_SS2_D_MARK,
2948};
2949static const unsigned int msiof2_txd_d_pins[] = {
2950 /* TXD */
2951 RCAR_GP_PIN(0, 11),
2952};
2953static const unsigned int msiof2_txd_d_mux[] = {
2954 MSIOF2_TXD_D_MARK,
2955};
2956static const unsigned int msiof2_rxd_d_pins[] = {
2957 /* RXD */
2958 RCAR_GP_PIN(0, 10),
2959};
2960static const unsigned int msiof2_rxd_d_mux[] = {
2961 MSIOF2_RXD_D_MARK,
2962};
2963/* - MSIOF3 ----------------------------------------------------------------- */
2964static const unsigned int msiof3_clk_a_pins[] = {
2965 /* SCK */
2966 RCAR_GP_PIN(0, 0),
2967};
2968static const unsigned int msiof3_clk_a_mux[] = {
2969 MSIOF3_SCK_A_MARK,
2970};
2971static const unsigned int msiof3_sync_a_pins[] = {
2972 /* SYNC */
2973 RCAR_GP_PIN(0, 1),
2974};
2975static const unsigned int msiof3_sync_a_mux[] = {
2976 MSIOF3_SYNC_A_MARK,
2977};
2978static const unsigned int msiof3_ss1_a_pins[] = {
2979 /* SS1 */
2980 RCAR_GP_PIN(0, 14),
2981};
2982static const unsigned int msiof3_ss1_a_mux[] = {
2983 MSIOF3_SS1_A_MARK,
2984};
2985static const unsigned int msiof3_ss2_a_pins[] = {
2986 /* SS2 */
2987 RCAR_GP_PIN(0, 15),
2988};
2989static const unsigned int msiof3_ss2_a_mux[] = {
2990 MSIOF3_SS2_A_MARK,
2991};
2992static const unsigned int msiof3_txd_a_pins[] = {
2993 /* TXD */
2994 RCAR_GP_PIN(0, 3),
2995};
2996static const unsigned int msiof3_txd_a_mux[] = {
2997 MSIOF3_TXD_A_MARK,
2998};
2999static const unsigned int msiof3_rxd_a_pins[] = {
3000 /* RXD */
3001 RCAR_GP_PIN(0, 2),
3002};
3003static const unsigned int msiof3_rxd_a_mux[] = {
3004 MSIOF3_RXD_A_MARK,
3005};
3006static const unsigned int msiof3_clk_b_pins[] = {
3007 /* SCK */
3008 RCAR_GP_PIN(1, 2),
3009};
3010static const unsigned int msiof3_clk_b_mux[] = {
3011 MSIOF3_SCK_B_MARK,
3012};
3013static const unsigned int msiof3_sync_b_pins[] = {
3014 /* SYNC */
3015 RCAR_GP_PIN(1, 0),
3016};
3017static const unsigned int msiof3_sync_b_mux[] = {
3018 MSIOF3_SYNC_B_MARK,
3019};
3020static const unsigned int msiof3_ss1_b_pins[] = {
3021 /* SS1 */
3022 RCAR_GP_PIN(1, 4),
3023};
3024static const unsigned int msiof3_ss1_b_mux[] = {
3025 MSIOF3_SS1_B_MARK,
3026};
3027static const unsigned int msiof3_ss2_b_pins[] = {
3028 /* SS2 */
3029 RCAR_GP_PIN(1, 5),
3030};
3031static const unsigned int msiof3_ss2_b_mux[] = {
3032 MSIOF3_SS2_B_MARK,
3033};
3034static const unsigned int msiof3_txd_b_pins[] = {
3035 /* TXD */
3036 RCAR_GP_PIN(1, 1),
3037};
3038static const unsigned int msiof3_txd_b_mux[] = {
3039 MSIOF3_TXD_B_MARK,
3040};
3041static const unsigned int msiof3_rxd_b_pins[] = {
3042 /* RXD */
3043 RCAR_GP_PIN(1, 3),
3044};
3045static const unsigned int msiof3_rxd_b_mux[] = {
3046 MSIOF3_RXD_B_MARK,
3047};
3048static const unsigned int msiof3_clk_c_pins[] = {
3049 /* SCK */
3050 RCAR_GP_PIN(1, 12),
3051};
3052static const unsigned int msiof3_clk_c_mux[] = {
3053 MSIOF3_SCK_C_MARK,
3054};
3055static const unsigned int msiof3_sync_c_pins[] = {
3056 /* SYNC */
3057 RCAR_GP_PIN(1, 13),
3058};
3059static const unsigned int msiof3_sync_c_mux[] = {
3060 MSIOF3_SYNC_C_MARK,
3061};
3062static const unsigned int msiof3_txd_c_pins[] = {
3063 /* TXD */
3064 RCAR_GP_PIN(1, 15),
3065};
3066static const unsigned int msiof3_txd_c_mux[] = {
3067 MSIOF3_TXD_C_MARK,
3068};
3069static const unsigned int msiof3_rxd_c_pins[] = {
3070 /* RXD */
3071 RCAR_GP_PIN(1, 14),
3072};
3073static const unsigned int msiof3_rxd_c_mux[] = {
3074 MSIOF3_RXD_C_MARK,
3075};
3076static const unsigned int msiof3_clk_d_pins[] = {
3077 /* SCK */
3078 RCAR_GP_PIN(1, 22),
3079};
3080static const unsigned int msiof3_clk_d_mux[] = {
3081 MSIOF3_SCK_D_MARK,
3082};
3083static const unsigned int msiof3_sync_d_pins[] = {
3084 /* SYNC */
3085 RCAR_GP_PIN(1, 23),
3086};
3087static const unsigned int msiof3_sync_d_mux[] = {
3088 MSIOF3_SYNC_D_MARK,
3089};
3090static const unsigned int msiof3_ss1_d_pins[] = {
3091 /* SS1 */
3092 RCAR_GP_PIN(1, 26),
3093};
3094static const unsigned int msiof3_ss1_d_mux[] = {
3095 MSIOF3_SS1_D_MARK,
3096};
3097static const unsigned int msiof3_txd_d_pins[] = {
3098 /* TXD */
3099 RCAR_GP_PIN(1, 25),
3100};
3101static const unsigned int msiof3_txd_d_mux[] = {
3102 MSIOF3_TXD_D_MARK,
3103};
3104static const unsigned int msiof3_rxd_d_pins[] = {
3105 /* RXD */
3106 RCAR_GP_PIN(1, 24),
3107};
3108static const unsigned int msiof3_rxd_d_mux[] = {
3109 MSIOF3_RXD_D_MARK,
3110};
3111
3112static const unsigned int msiof3_clk_e_pins[] = {
3113 /* SCK */
3114 RCAR_GP_PIN(2, 3),
3115};
3116static const unsigned int msiof3_clk_e_mux[] = {
3117 MSIOF3_SCK_E_MARK,
3118};
3119static const unsigned int msiof3_sync_e_pins[] = {
3120 /* SYNC */
3121 RCAR_GP_PIN(2, 2),
3122};
3123static const unsigned int msiof3_sync_e_mux[] = {
3124 MSIOF3_SYNC_E_MARK,
3125};
3126static const unsigned int msiof3_ss1_e_pins[] = {
3127 /* SS1 */
3128 RCAR_GP_PIN(2, 1),
3129};
3130static const unsigned int msiof3_ss1_e_mux[] = {
3131 MSIOF3_SS1_E_MARK,
3132};
3133static const unsigned int msiof3_ss2_e_pins[] = {
3134 /* SS1 */
3135 RCAR_GP_PIN(2, 0),
3136};
3137static const unsigned int msiof3_ss2_e_mux[] = {
3138 MSIOF3_SS2_E_MARK,
3139};
3140static const unsigned int msiof3_txd_e_pins[] = {
3141 /* TXD */
3142 RCAR_GP_PIN(2, 5),
3143};
3144static const unsigned int msiof3_txd_e_mux[] = {
3145 MSIOF3_TXD_E_MARK,
3146};
3147static const unsigned int msiof3_rxd_e_pins[] = {
3148 /* RXD */
3149 RCAR_GP_PIN(2, 4),
3150};
3151static const unsigned int msiof3_rxd_e_mux[] = {
3152 MSIOF3_RXD_E_MARK,
3153};
3154
3155/* - PWM0 --------------------------------------------------------------------*/
3156static const unsigned int pwm0_pins[] = {
3157 /* PWM */
3158 RCAR_GP_PIN(2, 6),
3159};
3160static const unsigned int pwm0_mux[] = {
3161 PWM0_MARK,
3162};
3163/* - PWM1 --------------------------------------------------------------------*/
3164static const unsigned int pwm1_a_pins[] = {
3165 /* PWM */
3166 RCAR_GP_PIN(2, 7),
3167};
3168static const unsigned int pwm1_a_mux[] = {
3169 PWM1_A_MARK,
3170};
3171static const unsigned int pwm1_b_pins[] = {
3172 /* PWM */
3173 RCAR_GP_PIN(1, 8),
3174};
3175static const unsigned int pwm1_b_mux[] = {
3176 PWM1_B_MARK,
3177};
3178/* - PWM2 --------------------------------------------------------------------*/
3179static const unsigned int pwm2_a_pins[] = {
3180 /* PWM */
3181 RCAR_GP_PIN(2, 8),
3182};
3183static const unsigned int pwm2_a_mux[] = {
3184 PWM2_A_MARK,
3185};
3186static const unsigned int pwm2_b_pins[] = {
3187 /* PWM */
3188 RCAR_GP_PIN(1, 11),
3189};
3190static const unsigned int pwm2_b_mux[] = {
3191 PWM2_B_MARK,
3192};
3193/* - PWM3 --------------------------------------------------------------------*/
3194static const unsigned int pwm3_a_pins[] = {
3195 /* PWM */
3196 RCAR_GP_PIN(1, 0),
3197};
3198static const unsigned int pwm3_a_mux[] = {
3199 PWM3_A_MARK,
3200};
3201static const unsigned int pwm3_b_pins[] = {
3202 /* PWM */
3203 RCAR_GP_PIN(2, 2),
3204};
3205static const unsigned int pwm3_b_mux[] = {
3206 PWM3_B_MARK,
3207};
3208/* - PWM4 --------------------------------------------------------------------*/
3209static const unsigned int pwm4_a_pins[] = {
3210 /* PWM */
3211 RCAR_GP_PIN(1, 1),
3212};
3213static const unsigned int pwm4_a_mux[] = {
3214 PWM4_A_MARK,
3215};
3216static const unsigned int pwm4_b_pins[] = {
3217 /* PWM */
3218 RCAR_GP_PIN(2, 3),
3219};
3220static const unsigned int pwm4_b_mux[] = {
3221 PWM4_B_MARK,
3222};
3223/* - PWM5 --------------------------------------------------------------------*/
3224static const unsigned int pwm5_a_pins[] = {
3225 /* PWM */
3226 RCAR_GP_PIN(1, 2),
3227};
3228static const unsigned int pwm5_a_mux[] = {
3229 PWM5_A_MARK,
3230};
3231static const unsigned int pwm5_b_pins[] = {
3232 /* PWM */
3233 RCAR_GP_PIN(2, 4),
3234};
3235static const unsigned int pwm5_b_mux[] = {
3236 PWM5_B_MARK,
3237};
3238/* - PWM6 --------------------------------------------------------------------*/
3239static const unsigned int pwm6_a_pins[] = {
3240 /* PWM */
3241 RCAR_GP_PIN(1, 3),
3242};
3243static const unsigned int pwm6_a_mux[] = {
3244 PWM6_A_MARK,
3245};
3246static const unsigned int pwm6_b_pins[] = {
3247 /* PWM */
3248 RCAR_GP_PIN(2, 5),
3249};
3250static const unsigned int pwm6_b_mux[] = {
3251 PWM6_B_MARK,
3252};
3253
3254/* - SCIF0 ------------------------------------------------------------------ */
3255static const unsigned int scif0_data_pins[] = {
3256 /* RX, TX */
3257 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3258};
3259static const unsigned int scif0_data_mux[] = {
3260 RX0_MARK, TX0_MARK,
3261};
3262static const unsigned int scif0_clk_pins[] = {
3263 /* SCK */
3264 RCAR_GP_PIN(5, 0),
3265};
3266static const unsigned int scif0_clk_mux[] = {
3267 SCK0_MARK,
3268};
3269static const unsigned int scif0_ctrl_pins[] = {
3270 /* RTS, CTS */
3271 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3272};
3273static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3274 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3275};
3276/* - SCIF1 ------------------------------------------------------------------ */
3277static const unsigned int scif1_data_a_pins[] = {
3278 /* RX, TX */
3279 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3280};
3281static const unsigned int scif1_data_a_mux[] = {
3282 RX1_A_MARK, TX1_A_MARK,
3283};
3284static const unsigned int scif1_clk_pins[] = {
3285 /* SCK */
3286 RCAR_GP_PIN(6, 21),
3287};
3288static const unsigned int scif1_clk_mux[] = {
3289 SCK1_MARK,
3290};
3291static const unsigned int scif1_ctrl_pins[] = {
3292 /* RTS, CTS */
3293 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3294};
3295static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3296 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3297};
3298
3299static const unsigned int scif1_data_b_pins[] = {
3300 /* RX, TX */
3301 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3302};
3303static const unsigned int scif1_data_b_mux[] = {
3304 RX1_B_MARK, TX1_B_MARK,
3305};
3306/* - SCIF2 ------------------------------------------------------------------ */
3307static const unsigned int scif2_data_a_pins[] = {
3308 /* RX, TX */
3309 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3310};
3311static const unsigned int scif2_data_a_mux[] = {
3312 RX2_A_MARK, TX2_A_MARK,
3313};
3314static const unsigned int scif2_clk_pins[] = {
3315 /* SCK */
3316 RCAR_GP_PIN(5, 9),
3317};
3318static const unsigned int scif2_clk_mux[] = {
3319 SCK2_MARK,
3320};
3321static const unsigned int scif2_data_b_pins[] = {
3322 /* RX, TX */
3323 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3324};
3325static const unsigned int scif2_data_b_mux[] = {
3326 RX2_B_MARK, TX2_B_MARK,
3327};
3328/* - SCIF3 ------------------------------------------------------------------ */
3329static const unsigned int scif3_data_a_pins[] = {
3330 /* RX, TX */
3331 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3332};
3333static const unsigned int scif3_data_a_mux[] = {
3334 RX3_A_MARK, TX3_A_MARK,
3335};
3336static const unsigned int scif3_clk_pins[] = {
3337 /* SCK */
3338 RCAR_GP_PIN(1, 22),
3339};
3340static const unsigned int scif3_clk_mux[] = {
3341 SCK3_MARK,
3342};
3343static const unsigned int scif3_ctrl_pins[] = {
3344 /* RTS, CTS */
3345 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3346};
3347static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3348 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3349};
3350static const unsigned int scif3_data_b_pins[] = {
3351 /* RX, TX */
3352 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3353};
3354static const unsigned int scif3_data_b_mux[] = {
3355 RX3_B_MARK, TX3_B_MARK,
3356};
3357/* - SCIF4 ------------------------------------------------------------------ */
3358static const unsigned int scif4_data_a_pins[] = {
3359 /* RX, TX */
3360 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3361};
3362static const unsigned int scif4_data_a_mux[] = {
3363 RX4_A_MARK, TX4_A_MARK,
3364};
3365static const unsigned int scif4_clk_a_pins[] = {
3366 /* SCK */
3367 RCAR_GP_PIN(2, 10),
3368};
3369static const unsigned int scif4_clk_a_mux[] = {
3370 SCK4_A_MARK,
3371};
3372static const unsigned int scif4_ctrl_a_pins[] = {
3373 /* RTS, CTS */
3374 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3375};
3376static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3377 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3378};
3379static const unsigned int scif4_data_b_pins[] = {
3380 /* RX, TX */
3381 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3382};
3383static const unsigned int scif4_data_b_mux[] = {
3384 RX4_B_MARK, TX4_B_MARK,
3385};
3386static const unsigned int scif4_clk_b_pins[] = {
3387 /* SCK */
3388 RCAR_GP_PIN(1, 5),
3389};
3390static const unsigned int scif4_clk_b_mux[] = {
3391 SCK4_B_MARK,
3392};
3393static const unsigned int scif4_ctrl_b_pins[] = {
3394 /* RTS, CTS */
3395 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3396};
3397static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3398 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3399};
3400static const unsigned int scif4_data_c_pins[] = {
3401 /* RX, TX */
3402 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3403};
3404static const unsigned int scif4_data_c_mux[] = {
3405 RX4_C_MARK, TX4_C_MARK,
3406};
3407static const unsigned int scif4_clk_c_pins[] = {
3408 /* SCK */
3409 RCAR_GP_PIN(0, 8),
3410};
3411static const unsigned int scif4_clk_c_mux[] = {
3412 SCK4_C_MARK,
3413};
3414static const unsigned int scif4_ctrl_c_pins[] = {
3415 /* RTS, CTS */
3416 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3417};
3418static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3419 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3420};
3421/* - SCIF5 ------------------------------------------------------------------ */
3422static const unsigned int scif5_data_a_pins[] = {
3423 /* RX, TX */
3424 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3425};
3426static const unsigned int scif5_data_a_mux[] = {
3427 RX5_A_MARK, TX5_A_MARK,
3428};
3429static const unsigned int scif5_clk_a_pins[] = {
3430 /* SCK */
3431 RCAR_GP_PIN(6, 21),
3432};
3433static const unsigned int scif5_clk_a_mux[] = {
3434 SCK5_A_MARK,
3435};
3436
3437static const unsigned int scif5_data_b_pins[] = {
3438 /* RX, TX */
3439 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3440};
3441static const unsigned int scif5_data_b_mux[] = {
3442 RX5_B_MARK, TX5_B_MARK,
3443};
3444static const unsigned int scif5_clk_b_pins[] = {
3445 /* SCK */
3446 RCAR_GP_PIN(5, 0),
3447};
3448static const unsigned int scif5_clk_b_mux[] = {
3449 SCK5_B_MARK,
3450};
3451
3452/* - SCIF Clock ------------------------------------------------------------- */
3453static const unsigned int scif_clk_a_pins[] = {
3454 /* SCIF_CLK */
3455 RCAR_GP_PIN(6, 23),
3456};
3457static const unsigned int scif_clk_a_mux[] = {
3458 SCIF_CLK_A_MARK,
3459};
3460static const unsigned int scif_clk_b_pins[] = {
3461 /* SCIF_CLK */
3462 RCAR_GP_PIN(5, 9),
3463};
3464static const unsigned int scif_clk_b_mux[] = {
3465 SCIF_CLK_B_MARK,
3466};
3467
3468/* - SDHI0 ------------------------------------------------------------------ */
3469static const unsigned int sdhi0_data1_pins[] = {
3470 /* D0 */
3471 RCAR_GP_PIN(3, 2),
3472};
3473static const unsigned int sdhi0_data1_mux[] = {
3474 SD0_DAT0_MARK,
3475};
3476static const unsigned int sdhi0_data4_pins[] = {
3477 /* D[0:3] */
3478 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3479 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3480};
3481static const unsigned int sdhi0_data4_mux[] = {
3482 SD0_DAT0_MARK, SD0_DAT1_MARK,
3483 SD0_DAT2_MARK, SD0_DAT3_MARK,
3484};
3485static const unsigned int sdhi0_ctrl_pins[] = {
3486 /* CLK, CMD */
3487 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3488};
3489static const unsigned int sdhi0_ctrl_mux[] = {
3490 SD0_CLK_MARK, SD0_CMD_MARK,
3491};
3492static const unsigned int sdhi0_cd_pins[] = {
3493 /* CD */
3494 RCAR_GP_PIN(3, 12),
3495};
3496static const unsigned int sdhi0_cd_mux[] = {
3497 SD0_CD_MARK,
3498};
3499static const unsigned int sdhi0_wp_pins[] = {
3500 /* WP */
3501 RCAR_GP_PIN(3, 13),
3502};
3503static const unsigned int sdhi0_wp_mux[] = {
3504 SD0_WP_MARK,
3505};
3506/* - SDHI1 ------------------------------------------------------------------ */
3507static const unsigned int sdhi1_data1_pins[] = {
3508 /* D0 */
3509 RCAR_GP_PIN(3, 8),
3510};
3511static const unsigned int sdhi1_data1_mux[] = {
3512 SD1_DAT0_MARK,
3513};
3514static const unsigned int sdhi1_data4_pins[] = {
3515 /* D[0:3] */
3516 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3517 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3518};
3519static const unsigned int sdhi1_data4_mux[] = {
3520 SD1_DAT0_MARK, SD1_DAT1_MARK,
3521 SD1_DAT2_MARK, SD1_DAT3_MARK,
3522};
3523static const unsigned int sdhi1_ctrl_pins[] = {
3524 /* CLK, CMD */
3525 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3526};
3527static const unsigned int sdhi1_ctrl_mux[] = {
3528 SD1_CLK_MARK, SD1_CMD_MARK,
3529};
3530static const unsigned int sdhi1_cd_pins[] = {
3531 /* CD */
3532 RCAR_GP_PIN(3, 14),
3533};
3534static const unsigned int sdhi1_cd_mux[] = {
3535 SD1_CD_MARK,
3536};
3537static const unsigned int sdhi1_wp_pins[] = {
3538 /* WP */
3539 RCAR_GP_PIN(3, 15),
3540};
3541static const unsigned int sdhi1_wp_mux[] = {
3542 SD1_WP_MARK,
3543};
3544/* - SDHI2 ------------------------------------------------------------------ */
3545static const unsigned int sdhi2_data1_pins[] = {
3546 /* D0 */
3547 RCAR_GP_PIN(4, 2),
3548};
3549static const unsigned int sdhi2_data1_mux[] = {
3550 SD2_DAT0_MARK,
3551};
3552static const unsigned int sdhi2_data4_pins[] = {
3553 /* D[0:3] */
3554 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3555 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3556};
3557static const unsigned int sdhi2_data4_mux[] = {
3558 SD2_DAT0_MARK, SD2_DAT1_MARK,
3559 SD2_DAT2_MARK, SD2_DAT3_MARK,
3560};
3561static const unsigned int sdhi2_data8_pins[] = {
3562 /* D[0:7] */
3563 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3564 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3565 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3566 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3567};
3568static const unsigned int sdhi2_data8_mux[] = {
3569 SD2_DAT0_MARK, SD2_DAT1_MARK,
3570 SD2_DAT2_MARK, SD2_DAT3_MARK,
3571 SD2_DAT4_MARK, SD2_DAT5_MARK,
3572 SD2_DAT6_MARK, SD2_DAT7_MARK,
3573};
3574static const unsigned int sdhi2_ctrl_pins[] = {
3575 /* CLK, CMD */
3576 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3577};
3578static const unsigned int sdhi2_ctrl_mux[] = {
3579 SD2_CLK_MARK, SD2_CMD_MARK,
3580};
3581static const unsigned int sdhi2_cd_a_pins[] = {
3582 /* CD */
3583 RCAR_GP_PIN(4, 13),
3584};
3585static const unsigned int sdhi2_cd_a_mux[] = {
3586 SD2_CD_A_MARK,
3587};
3588static const unsigned int sdhi2_cd_b_pins[] = {
3589 /* CD */
3590 RCAR_GP_PIN(5, 10),
3591};
3592static const unsigned int sdhi2_cd_b_mux[] = {
3593 SD2_CD_B_MARK,
3594};
3595static const unsigned int sdhi2_wp_a_pins[] = {
3596 /* WP */
3597 RCAR_GP_PIN(4, 14),
3598};
3599static const unsigned int sdhi2_wp_a_mux[] = {
3600 SD2_WP_A_MARK,
3601};
3602static const unsigned int sdhi2_wp_b_pins[] = {
3603 /* WP */
3604 RCAR_GP_PIN(5, 11),
3605};
3606static const unsigned int sdhi2_wp_b_mux[] = {
3607 SD2_WP_B_MARK,
3608};
3609static const unsigned int sdhi2_ds_pins[] = {
3610 /* DS */
3611 RCAR_GP_PIN(4, 6),
3612};
3613static const unsigned int sdhi2_ds_mux[] = {
3614 SD2_DS_MARK,
3615};
3616/* - SDHI3 ------------------------------------------------------------------ */
3617static const unsigned int sdhi3_data1_pins[] = {
3618 /* D0 */
3619 RCAR_GP_PIN(4, 9),
3620};
3621static const unsigned int sdhi3_data1_mux[] = {
3622 SD3_DAT0_MARK,
3623};
3624static const unsigned int sdhi3_data4_pins[] = {
3625 /* D[0:3] */
3626 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3627 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3628};
3629static const unsigned int sdhi3_data4_mux[] = {
3630 SD3_DAT0_MARK, SD3_DAT1_MARK,
3631 SD3_DAT2_MARK, SD3_DAT3_MARK,
3632};
3633static const unsigned int sdhi3_data8_pins[] = {
3634 /* D[0:7] */
3635 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3636 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3637 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3638 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3639};
3640static const unsigned int sdhi3_data8_mux[] = {
3641 SD3_DAT0_MARK, SD3_DAT1_MARK,
3642 SD3_DAT2_MARK, SD3_DAT3_MARK,
3643 SD3_DAT4_MARK, SD3_DAT5_MARK,
3644 SD3_DAT6_MARK, SD3_DAT7_MARK,
3645};
3646static const unsigned int sdhi3_ctrl_pins[] = {
3647 /* CLK, CMD */
3648 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3649};
3650static const unsigned int sdhi3_ctrl_mux[] = {
3651 SD3_CLK_MARK, SD3_CMD_MARK,
3652};
3653static const unsigned int sdhi3_cd_pins[] = {
3654 /* CD */
3655 RCAR_GP_PIN(4, 15),
3656};
3657static const unsigned int sdhi3_cd_mux[] = {
3658 SD3_CD_MARK,
3659};
3660static const unsigned int sdhi3_wp_pins[] = {
3661 /* WP */
3662 RCAR_GP_PIN(4, 16),
3663};
3664static const unsigned int sdhi3_wp_mux[] = {
3665 SD3_WP_MARK,
3666};
3667static const unsigned int sdhi3_ds_pins[] = {
3668 /* DS */
3669 RCAR_GP_PIN(4, 17),
3670};
3671static const unsigned int sdhi3_ds_mux[] = {
3672 SD3_DS_MARK,
3673};
3674
3675/* - SSI -------------------------------------------------------------------- */
3676static const unsigned int ssi0_data_pins[] = {
3677 /* SDATA */
3678 RCAR_GP_PIN(6, 2),
3679};
3680static const unsigned int ssi0_data_mux[] = {
3681 SSI_SDATA0_MARK,
3682};
3683static const unsigned int ssi01239_ctrl_pins[] = {
3684 /* SCK, WS */
3685 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3686};
3687static const unsigned int ssi01239_ctrl_mux[] = {
3688 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3689};
3690static const unsigned int ssi1_data_a_pins[] = {
3691 /* SDATA */
3692 RCAR_GP_PIN(6, 3),
3693};
3694static const unsigned int ssi1_data_a_mux[] = {
3695 SSI_SDATA1_A_MARK,
3696};
3697static const unsigned int ssi1_data_b_pins[] = {
3698 /* SDATA */
3699 RCAR_GP_PIN(5, 12),
3700};
3701static const unsigned int ssi1_data_b_mux[] = {
3702 SSI_SDATA1_B_MARK,
3703};
3704static const unsigned int ssi1_ctrl_a_pins[] = {
3705 /* SCK, WS */
3706 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3707};
3708static const unsigned int ssi1_ctrl_a_mux[] = {
3709 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3710};
3711static const unsigned int ssi1_ctrl_b_pins[] = {
3712 /* SCK, WS */
3713 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3714};
3715static const unsigned int ssi1_ctrl_b_mux[] = {
3716 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3717};
3718static const unsigned int ssi2_data_a_pins[] = {
3719 /* SDATA */
3720 RCAR_GP_PIN(6, 4),
3721};
3722static const unsigned int ssi2_data_a_mux[] = {
3723 SSI_SDATA2_A_MARK,
3724};
3725static const unsigned int ssi2_data_b_pins[] = {
3726 /* SDATA */
3727 RCAR_GP_PIN(5, 13),
3728};
3729static const unsigned int ssi2_data_b_mux[] = {
3730 SSI_SDATA2_B_MARK,
3731};
3732static const unsigned int ssi2_ctrl_a_pins[] = {
3733 /* SCK, WS */
3734 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3735};
3736static const unsigned int ssi2_ctrl_a_mux[] = {
3737 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3738};
3739static const unsigned int ssi2_ctrl_b_pins[] = {
3740 /* SCK, WS */
3741 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3742};
3743static const unsigned int ssi2_ctrl_b_mux[] = {
3744 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3745};
3746static const unsigned int ssi3_data_pins[] = {
3747 /* SDATA */
3748 RCAR_GP_PIN(6, 7),
3749};
3750static const unsigned int ssi3_data_mux[] = {
3751 SSI_SDATA3_MARK,
3752};
3753static const unsigned int ssi349_ctrl_pins[] = {
3754 /* SCK, WS */
3755 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3756};
3757static const unsigned int ssi349_ctrl_mux[] = {
3758 SSI_SCK349_MARK, SSI_WS349_MARK,
3759};
3760static const unsigned int ssi4_data_pins[] = {
3761 /* SDATA */
3762 RCAR_GP_PIN(6, 10),
3763};
3764static const unsigned int ssi4_data_mux[] = {
3765 SSI_SDATA4_MARK,
3766};
3767static const unsigned int ssi4_ctrl_pins[] = {
3768 /* SCK, WS */
3769 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3770};
3771static const unsigned int ssi4_ctrl_mux[] = {
3772 SSI_SCK4_MARK, SSI_WS4_MARK,
3773};
3774static const unsigned int ssi5_data_pins[] = {
3775 /* SDATA */
3776 RCAR_GP_PIN(6, 13),
3777};
3778static const unsigned int ssi5_data_mux[] = {
3779 SSI_SDATA5_MARK,
3780};
3781static const unsigned int ssi5_ctrl_pins[] = {
3782 /* SCK, WS */
3783 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3784};
3785static const unsigned int ssi5_ctrl_mux[] = {
3786 SSI_SCK5_MARK, SSI_WS5_MARK,
3787};
3788static const unsigned int ssi6_data_pins[] = {
3789 /* SDATA */
3790 RCAR_GP_PIN(6, 16),
3791};
3792static const unsigned int ssi6_data_mux[] = {
3793 SSI_SDATA6_MARK,
3794};
3795static const unsigned int ssi6_ctrl_pins[] = {
3796 /* SCK, WS */
3797 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3798};
3799static const unsigned int ssi6_ctrl_mux[] = {
3800 SSI_SCK6_MARK, SSI_WS6_MARK,
3801};
3802static const unsigned int ssi7_data_pins[] = {
3803 /* SDATA */
3804 RCAR_GP_PIN(6, 19),
3805};
3806static const unsigned int ssi7_data_mux[] = {
3807 SSI_SDATA7_MARK,
3808};
3809static const unsigned int ssi78_ctrl_pins[] = {
3810 /* SCK, WS */
3811 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3812};
3813static const unsigned int ssi78_ctrl_mux[] = {
3814 SSI_SCK78_MARK, SSI_WS78_MARK,
3815};
3816static const unsigned int ssi8_data_pins[] = {
3817 /* SDATA */
3818 RCAR_GP_PIN(6, 20),
3819};
3820static const unsigned int ssi8_data_mux[] = {
3821 SSI_SDATA8_MARK,
3822};
3823static const unsigned int ssi9_data_a_pins[] = {
3824 /* SDATA */
3825 RCAR_GP_PIN(6, 21),
3826};
3827static const unsigned int ssi9_data_a_mux[] = {
3828 SSI_SDATA9_A_MARK,
3829};
3830static const unsigned int ssi9_data_b_pins[] = {
3831 /* SDATA */
3832 RCAR_GP_PIN(5, 14),
3833};
3834static const unsigned int ssi9_data_b_mux[] = {
3835 SSI_SDATA9_B_MARK,
3836};
3837static const unsigned int ssi9_ctrl_a_pins[] = {
3838 /* SCK, WS */
3839 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3840};
3841static const unsigned int ssi9_ctrl_a_mux[] = {
3842 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3843};
3844static const unsigned int ssi9_ctrl_b_pins[] = {
3845 /* SCK, WS */
3846 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3847};
3848static const unsigned int ssi9_ctrl_b_mux[] = {
3849 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3850};
3851
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3852/* - TMU -------------------------------------------------------------------- */
3853static const unsigned int tmu_tclk1_a_pins[] = {
3854 /* TCLK */
3855 RCAR_GP_PIN(6, 23),
3856};
3857static const unsigned int tmu_tclk1_a_mux[] = {
3858 TCLK1_A_MARK,
3859};
3860static const unsigned int tmu_tclk1_b_pins[] = {
3861 /* TCLK */
3862 RCAR_GP_PIN(5, 19),
3863};
3864static const unsigned int tmu_tclk1_b_mux[] = {
3865 TCLK1_B_MARK,
3866};
3867static const unsigned int tmu_tclk2_a_pins[] = {
3868 /* TCLK */
3869 RCAR_GP_PIN(6, 19),
3870};
3871static const unsigned int tmu_tclk2_a_mux[] = {
3872 TCLK2_A_MARK,
3873};
3874static const unsigned int tmu_tclk2_b_pins[] = {
3875 /* TCLK */
3876 RCAR_GP_PIN(6, 28),
3877};
3878static const unsigned int tmu_tclk2_b_mux[] = {
3879 TCLK2_B_MARK,
3880};
3881
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3882/* - USB0 ------------------------------------------------------------------- */
3883static const unsigned int usb0_pins[] = {
3884 /* PWEN, OVC */
3885 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3886};
3887static const unsigned int usb0_mux[] = {
3888 USB0_PWEN_MARK, USB0_OVC_MARK,
3889};
3890/* - USB1 ------------------------------------------------------------------- */
3891static const unsigned int usb1_pins[] = {
3892 /* PWEN, OVC */
3893 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3894};
3895static const unsigned int usb1_mux[] = {
3896 USB1_PWEN_MARK, USB1_OVC_MARK,
3897};
3898
3899/* - USB30 ------------------------------------------------------------------ */
3900static const unsigned int usb30_pins[] = {
3901 /* PWEN, OVC */
3902 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3903};
3904static const unsigned int usb30_mux[] = {
3905 USB30_PWEN_MARK, USB30_OVC_MARK,
3906};
3907
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3908/* - VIN4 ------------------------------------------------------------------- */
3909static const unsigned int vin4_data18_a_pins[] = {
3910 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3911 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3912 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3913 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3914 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3915 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3916 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3917 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3918 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3919};
3920static const unsigned int vin4_data18_a_mux[] = {
3921 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3922 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3923 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3924 VI4_DATA10_MARK, VI4_DATA11_MARK,
3925 VI4_DATA12_MARK, VI4_DATA13_MARK,
3926 VI4_DATA14_MARK, VI4_DATA15_MARK,
3927 VI4_DATA18_MARK, VI4_DATA19_MARK,
3928 VI4_DATA20_MARK, VI4_DATA21_MARK,
3929 VI4_DATA22_MARK, VI4_DATA23_MARK,
3930};
3931static const unsigned int vin4_data18_b_pins[] = {
3932 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3933 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3934 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3935 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3936 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3937 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3938 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3939 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3940 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3941};
3942static const unsigned int vin4_data18_b_mux[] = {
3943 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3944 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3945 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3946 VI4_DATA10_MARK, VI4_DATA11_MARK,
3947 VI4_DATA12_MARK, VI4_DATA13_MARK,
3948 VI4_DATA14_MARK, VI4_DATA15_MARK,
3949 VI4_DATA18_MARK, VI4_DATA19_MARK,
3950 VI4_DATA20_MARK, VI4_DATA21_MARK,
3951 VI4_DATA22_MARK, VI4_DATA23_MARK,
3952};
3953static const union vin_data vin4_data_a_pins = {
3954 .data24 = {
3955 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3956 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3957 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3958 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3959 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3960 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3961 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3962 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3963 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3964 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3965 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3966 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3967 },
3968};
3969static const union vin_data vin4_data_a_mux = {
3970 .data24 = {
3971 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3972 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3973 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3974 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3975 VI4_DATA8_MARK, VI4_DATA9_MARK,
3976 VI4_DATA10_MARK, VI4_DATA11_MARK,
3977 VI4_DATA12_MARK, VI4_DATA13_MARK,
3978 VI4_DATA14_MARK, VI4_DATA15_MARK,
3979 VI4_DATA16_MARK, VI4_DATA17_MARK,
3980 VI4_DATA18_MARK, VI4_DATA19_MARK,
3981 VI4_DATA20_MARK, VI4_DATA21_MARK,
3982 VI4_DATA22_MARK, VI4_DATA23_MARK,
3983 },
3984};
3985static const union vin_data vin4_data_b_pins = {
3986 .data24 = {
3987 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3988 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3989 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3990 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3991 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3992 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3993 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3994 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3995 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3996 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3997 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3998 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3999 },
4000};
4001static const union vin_data vin4_data_b_mux = {
4002 .data24 = {
4003 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4004 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4005 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4006 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4007 VI4_DATA8_MARK, VI4_DATA9_MARK,
4008 VI4_DATA10_MARK, VI4_DATA11_MARK,
4009 VI4_DATA12_MARK, VI4_DATA13_MARK,
4010 VI4_DATA14_MARK, VI4_DATA15_MARK,
4011 VI4_DATA16_MARK, VI4_DATA17_MARK,
4012 VI4_DATA18_MARK, VI4_DATA19_MARK,
4013 VI4_DATA20_MARK, VI4_DATA21_MARK,
4014 VI4_DATA22_MARK, VI4_DATA23_MARK,
4015 },
4016};
4017static const unsigned int vin4_sync_pins[] = {
4018 /* HSYNC#, VSYNC# */
4019 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4020};
4021static const unsigned int vin4_sync_mux[] = {
4022 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4023};
4024static const unsigned int vin4_field_pins[] = {
4025 /* FIELD */
4026 RCAR_GP_PIN(1, 16),
4027};
4028static const unsigned int vin4_field_mux[] = {
4029 VI4_FIELD_MARK,
4030};
4031static const unsigned int vin4_clkenb_pins[] = {
4032 /* CLKENB */
4033 RCAR_GP_PIN(1, 19),
4034};
4035static const unsigned int vin4_clkenb_mux[] = {
4036 VI4_CLKENB_MARK,
4037};
4038static const unsigned int vin4_clk_pins[] = {
4039 /* CLK */
4040 RCAR_GP_PIN(1, 27),
4041};
4042static const unsigned int vin4_clk_mux[] = {
4043 VI4_CLK_MARK,
4044};
4045
4046/* - VIN5 ------------------------------------------------------------------- */
4047static const unsigned int vin5_data8_pins[] = {
4048 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4049 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4050 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4051 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4052};
4053static const unsigned int vin5_data8_mux[] = {
4054 VI5_DATA0_MARK, VI5_DATA1_MARK,
4055 VI5_DATA2_MARK, VI5_DATA3_MARK,
4056 VI5_DATA4_MARK, VI5_DATA5_MARK,
4057 VI5_DATA6_MARK, VI5_DATA7_MARK,
4058};
4059static const unsigned int vin5_data10_pins[] = {
4060 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4061 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4062 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4063 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4064 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4065};
4066static const unsigned int vin5_data10_mux[] = {
4067 VI5_DATA0_MARK, VI5_DATA1_MARK,
4068 VI5_DATA2_MARK, VI5_DATA3_MARK,
4069 VI5_DATA4_MARK, VI5_DATA5_MARK,
4070 VI5_DATA6_MARK, VI5_DATA7_MARK,
4071 VI5_DATA8_MARK, VI5_DATA9_MARK,
4072};
4073static const unsigned int vin5_data12_pins[] = {
4074 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4075 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4076 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4077 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4078 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4079 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4080};
4081static const unsigned int vin5_data12_mux[] = {
4082 VI5_DATA0_MARK, VI5_DATA1_MARK,
4083 VI5_DATA2_MARK, VI5_DATA3_MARK,
4084 VI5_DATA4_MARK, VI5_DATA5_MARK,
4085 VI5_DATA6_MARK, VI5_DATA7_MARK,
4086 VI5_DATA8_MARK, VI5_DATA9_MARK,
4087 VI5_DATA10_MARK, VI5_DATA11_MARK,
4088};
4089static const unsigned int vin5_data16_pins[] = {
4090 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4091 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4092 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4093 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4094 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4095 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4096 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4097 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4098};
4099static const unsigned int vin5_data16_mux[] = {
4100 VI5_DATA0_MARK, VI5_DATA1_MARK,
4101 VI5_DATA2_MARK, VI5_DATA3_MARK,
4102 VI5_DATA4_MARK, VI5_DATA5_MARK,
4103 VI5_DATA6_MARK, VI5_DATA7_MARK,
4104 VI5_DATA8_MARK, VI5_DATA9_MARK,
4105 VI5_DATA10_MARK, VI5_DATA11_MARK,
4106 VI5_DATA12_MARK, VI5_DATA13_MARK,
4107 VI5_DATA14_MARK, VI5_DATA15_MARK,
4108};
4109static const unsigned int vin5_sync_pins[] = {
4110 /* HSYNC#, VSYNC# */
4111 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4112};
4113static const unsigned int vin5_sync_mux[] = {
4114 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4115};
4116static const unsigned int vin5_field_pins[] = {
4117 RCAR_GP_PIN(1, 11),
4118};
4119static const unsigned int vin5_field_mux[] = {
4120 /* FIELD */
4121 VI5_FIELD_MARK,
4122};
4123static const unsigned int vin5_clkenb_pins[] = {
4124 RCAR_GP_PIN(1, 20),
4125};
4126static const unsigned int vin5_clkenb_mux[] = {
4127 /* CLKENB */
4128 VI5_CLKENB_MARK,
4129};
4130static const unsigned int vin5_clk_pins[] = {
4131 RCAR_GP_PIN(1, 21),
4132};
4133static const unsigned int vin5_clk_mux[] = {
4134 /* CLK */
4135 VI5_CLK_MARK,
4136};
4137
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4138static const struct sh_pfc_pin_group pinmux_groups[] = {
4139 SH_PFC_PIN_GROUP(audio_clk_a_a),
4140 SH_PFC_PIN_GROUP(audio_clk_a_b),
4141 SH_PFC_PIN_GROUP(audio_clk_a_c),
4142 SH_PFC_PIN_GROUP(audio_clk_b_a),
4143 SH_PFC_PIN_GROUP(audio_clk_b_b),
4144 SH_PFC_PIN_GROUP(audio_clk_c_a),
4145 SH_PFC_PIN_GROUP(audio_clk_c_b),
4146 SH_PFC_PIN_GROUP(audio_clkout_a),
4147 SH_PFC_PIN_GROUP(audio_clkout_b),
4148 SH_PFC_PIN_GROUP(audio_clkout_c),
4149 SH_PFC_PIN_GROUP(audio_clkout_d),
4150 SH_PFC_PIN_GROUP(audio_clkout1_a),
4151 SH_PFC_PIN_GROUP(audio_clkout1_b),
4152 SH_PFC_PIN_GROUP(audio_clkout2_a),
4153 SH_PFC_PIN_GROUP(audio_clkout2_b),
4154 SH_PFC_PIN_GROUP(audio_clkout3_a),
4155 SH_PFC_PIN_GROUP(audio_clkout3_b),
4156 SH_PFC_PIN_GROUP(avb_link),
4157 SH_PFC_PIN_GROUP(avb_magic),
4158 SH_PFC_PIN_GROUP(avb_phy_int),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4159 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4160 SH_PFC_PIN_GROUP(avb_mdio),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4161 SH_PFC_PIN_GROUP(avb_mii),
4162 SH_PFC_PIN_GROUP(avb_avtp_pps),
4163 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4164 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4165 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4166 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4167 SH_PFC_PIN_GROUP(can0_data_a),
4168 SH_PFC_PIN_GROUP(can0_data_b),
4169 SH_PFC_PIN_GROUP(can1_data),
4170 SH_PFC_PIN_GROUP(can_clk),
4171 SH_PFC_PIN_GROUP(canfd0_data_a),
4172 SH_PFC_PIN_GROUP(canfd0_data_b),
4173 SH_PFC_PIN_GROUP(canfd1_data),
4174 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4175 SH_PFC_PIN_GROUP(drif0_data0_a),
4176 SH_PFC_PIN_GROUP(drif0_data1_a),
4177 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4178 SH_PFC_PIN_GROUP(drif0_data0_b),
4179 SH_PFC_PIN_GROUP(drif0_data1_b),
4180 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4181 SH_PFC_PIN_GROUP(drif0_data0_c),
4182 SH_PFC_PIN_GROUP(drif0_data1_c),
4183 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4184 SH_PFC_PIN_GROUP(drif1_data0_a),
4185 SH_PFC_PIN_GROUP(drif1_data1_a),
4186 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4187 SH_PFC_PIN_GROUP(drif1_data0_b),
4188 SH_PFC_PIN_GROUP(drif1_data1_b),
4189 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4190 SH_PFC_PIN_GROUP(drif1_data0_c),
4191 SH_PFC_PIN_GROUP(drif1_data1_c),
4192 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4193 SH_PFC_PIN_GROUP(drif2_data0_a),
4194 SH_PFC_PIN_GROUP(drif2_data1_a),
4195 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4196 SH_PFC_PIN_GROUP(drif2_data0_b),
4197 SH_PFC_PIN_GROUP(drif2_data1_b),
4198 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4199 SH_PFC_PIN_GROUP(drif3_data0_a),
4200 SH_PFC_PIN_GROUP(drif3_data1_a),
4201 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4202 SH_PFC_PIN_GROUP(drif3_data0_b),
4203 SH_PFC_PIN_GROUP(drif3_data1_b),
4204 SH_PFC_PIN_GROUP(du_rgb666),
4205 SH_PFC_PIN_GROUP(du_rgb888),
4206 SH_PFC_PIN_GROUP(du_clk_out_0),
4207 SH_PFC_PIN_GROUP(du_clk_out_1),
4208 SH_PFC_PIN_GROUP(du_sync),
4209 SH_PFC_PIN_GROUP(du_oddf),
4210 SH_PFC_PIN_GROUP(du_cde),
4211 SH_PFC_PIN_GROUP(du_disp),
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]4212 SH_PFC_PIN_GROUP(gp7_02),
4213 SH_PFC_PIN_GROUP(gp7_03),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4214 SH_PFC_PIN_GROUP(hscif0_data),
4215 SH_PFC_PIN_GROUP(hscif0_clk),
4216 SH_PFC_PIN_GROUP(hscif0_ctrl),
4217 SH_PFC_PIN_GROUP(hscif1_data_a),
4218 SH_PFC_PIN_GROUP(hscif1_clk_a),
4219 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4220 SH_PFC_PIN_GROUP(hscif1_data_b),
4221 SH_PFC_PIN_GROUP(hscif1_clk_b),
4222 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4223 SH_PFC_PIN_GROUP(hscif2_data_a),
4224 SH_PFC_PIN_GROUP(hscif2_clk_a),
4225 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4226 SH_PFC_PIN_GROUP(hscif2_data_b),
4227 SH_PFC_PIN_GROUP(hscif2_clk_b),
4228 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4229 SH_PFC_PIN_GROUP(hscif2_data_c),
4230 SH_PFC_PIN_GROUP(hscif2_clk_c),
4231 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4232 SH_PFC_PIN_GROUP(hscif3_data_a),
4233 SH_PFC_PIN_GROUP(hscif3_clk),
4234 SH_PFC_PIN_GROUP(hscif3_ctrl),
4235 SH_PFC_PIN_GROUP(hscif3_data_b),
4236 SH_PFC_PIN_GROUP(hscif3_data_c),
4237 SH_PFC_PIN_GROUP(hscif3_data_d),
4238 SH_PFC_PIN_GROUP(hscif4_data_a),
4239 SH_PFC_PIN_GROUP(hscif4_clk),
4240 SH_PFC_PIN_GROUP(hscif4_ctrl),
4241 SH_PFC_PIN_GROUP(hscif4_data_b),
4242 SH_PFC_PIN_GROUP(i2c1_a),
4243 SH_PFC_PIN_GROUP(i2c1_b),
4244 SH_PFC_PIN_GROUP(i2c2_a),
4245 SH_PFC_PIN_GROUP(i2c2_b),
4246 SH_PFC_PIN_GROUP(i2c6_a),
4247 SH_PFC_PIN_GROUP(i2c6_b),
4248 SH_PFC_PIN_GROUP(i2c6_c),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4249 SH_PFC_PIN_GROUP(intc_ex_irq0),
4250 SH_PFC_PIN_GROUP(intc_ex_irq1),
4251 SH_PFC_PIN_GROUP(intc_ex_irq2),
4252 SH_PFC_PIN_GROUP(intc_ex_irq3),
4253 SH_PFC_PIN_GROUP(intc_ex_irq4),
4254 SH_PFC_PIN_GROUP(intc_ex_irq5),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4255 SH_PFC_PIN_GROUP(msiof0_clk),
4256 SH_PFC_PIN_GROUP(msiof0_sync),
4257 SH_PFC_PIN_GROUP(msiof0_ss1),
4258 SH_PFC_PIN_GROUP(msiof0_ss2),
4259 SH_PFC_PIN_GROUP(msiof0_txd),
4260 SH_PFC_PIN_GROUP(msiof0_rxd),
4261 SH_PFC_PIN_GROUP(msiof1_clk_a),
4262 SH_PFC_PIN_GROUP(msiof1_sync_a),
4263 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4264 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4265 SH_PFC_PIN_GROUP(msiof1_txd_a),
4266 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4267 SH_PFC_PIN_GROUP(msiof1_clk_b),
4268 SH_PFC_PIN_GROUP(msiof1_sync_b),
4269 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4270 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4271 SH_PFC_PIN_GROUP(msiof1_txd_b),
4272 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4273 SH_PFC_PIN_GROUP(msiof1_clk_c),
4274 SH_PFC_PIN_GROUP(msiof1_sync_c),
4275 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4276 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4277 SH_PFC_PIN_GROUP(msiof1_txd_c),
4278 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4279 SH_PFC_PIN_GROUP(msiof1_clk_d),
4280 SH_PFC_PIN_GROUP(msiof1_sync_d),
4281 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4282 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4283 SH_PFC_PIN_GROUP(msiof1_txd_d),
4284 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4285 SH_PFC_PIN_GROUP(msiof1_clk_e),
4286 SH_PFC_PIN_GROUP(msiof1_sync_e),
4287 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4288 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4289 SH_PFC_PIN_GROUP(msiof1_txd_e),
4290 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4291 SH_PFC_PIN_GROUP(msiof1_clk_f),
4292 SH_PFC_PIN_GROUP(msiof1_sync_f),
4293 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4294 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4295 SH_PFC_PIN_GROUP(msiof1_txd_f),
4296 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4297 SH_PFC_PIN_GROUP(msiof1_clk_g),
4298 SH_PFC_PIN_GROUP(msiof1_sync_g),
4299 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4300 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4301 SH_PFC_PIN_GROUP(msiof1_txd_g),
4302 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4303 SH_PFC_PIN_GROUP(msiof2_clk_a),
4304 SH_PFC_PIN_GROUP(msiof2_sync_a),
4305 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4306 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4307 SH_PFC_PIN_GROUP(msiof2_txd_a),
4308 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4309 SH_PFC_PIN_GROUP(msiof2_clk_b),
4310 SH_PFC_PIN_GROUP(msiof2_sync_b),
4311 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4312 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4313 SH_PFC_PIN_GROUP(msiof2_txd_b),
4314 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4315 SH_PFC_PIN_GROUP(msiof2_clk_c),
4316 SH_PFC_PIN_GROUP(msiof2_sync_c),
4317 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4318 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4319 SH_PFC_PIN_GROUP(msiof2_txd_c),
4320 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4321 SH_PFC_PIN_GROUP(msiof2_clk_d),
4322 SH_PFC_PIN_GROUP(msiof2_sync_d),
4323 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4324 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4325 SH_PFC_PIN_GROUP(msiof2_txd_d),
4326 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4327 SH_PFC_PIN_GROUP(msiof3_clk_a),
4328 SH_PFC_PIN_GROUP(msiof3_sync_a),
4329 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4330 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4331 SH_PFC_PIN_GROUP(msiof3_txd_a),
4332 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4333 SH_PFC_PIN_GROUP(msiof3_clk_b),
4334 SH_PFC_PIN_GROUP(msiof3_sync_b),
4335 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4336 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4337 SH_PFC_PIN_GROUP(msiof3_txd_b),
4338 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4339 SH_PFC_PIN_GROUP(msiof3_clk_c),
4340 SH_PFC_PIN_GROUP(msiof3_sync_c),
4341 SH_PFC_PIN_GROUP(msiof3_txd_c),
4342 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4343 SH_PFC_PIN_GROUP(msiof3_clk_d),
4344 SH_PFC_PIN_GROUP(msiof3_sync_d),
4345 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4346 SH_PFC_PIN_GROUP(msiof3_txd_d),
4347 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4348 SH_PFC_PIN_GROUP(msiof3_clk_e),
4349 SH_PFC_PIN_GROUP(msiof3_sync_e),
4350 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4351 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4352 SH_PFC_PIN_GROUP(msiof3_txd_e),
4353 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4354 SH_PFC_PIN_GROUP(pwm0),
4355 SH_PFC_PIN_GROUP(pwm1_a),
4356 SH_PFC_PIN_GROUP(pwm1_b),
4357 SH_PFC_PIN_GROUP(pwm2_a),
4358 SH_PFC_PIN_GROUP(pwm2_b),
4359 SH_PFC_PIN_GROUP(pwm3_a),
4360 SH_PFC_PIN_GROUP(pwm3_b),
4361 SH_PFC_PIN_GROUP(pwm4_a),
4362 SH_PFC_PIN_GROUP(pwm4_b),
4363 SH_PFC_PIN_GROUP(pwm5_a),
4364 SH_PFC_PIN_GROUP(pwm5_b),
4365 SH_PFC_PIN_GROUP(pwm6_a),
4366 SH_PFC_PIN_GROUP(pwm6_b),
4367 SH_PFC_PIN_GROUP(scif0_data),
4368 SH_PFC_PIN_GROUP(scif0_clk),
4369 SH_PFC_PIN_GROUP(scif0_ctrl),
4370 SH_PFC_PIN_GROUP(scif1_data_a),
4371 SH_PFC_PIN_GROUP(scif1_clk),
4372 SH_PFC_PIN_GROUP(scif1_ctrl),
4373 SH_PFC_PIN_GROUP(scif1_data_b),
4374 SH_PFC_PIN_GROUP(scif2_data_a),
4375 SH_PFC_PIN_GROUP(scif2_clk),
4376 SH_PFC_PIN_GROUP(scif2_data_b),
4377 SH_PFC_PIN_GROUP(scif3_data_a),
4378 SH_PFC_PIN_GROUP(scif3_clk),
4379 SH_PFC_PIN_GROUP(scif3_ctrl),
4380 SH_PFC_PIN_GROUP(scif3_data_b),
4381 SH_PFC_PIN_GROUP(scif4_data_a),
4382 SH_PFC_PIN_GROUP(scif4_clk_a),
4383 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4384 SH_PFC_PIN_GROUP(scif4_data_b),
4385 SH_PFC_PIN_GROUP(scif4_clk_b),
4386 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4387 SH_PFC_PIN_GROUP(scif4_data_c),
4388 SH_PFC_PIN_GROUP(scif4_clk_c),
4389 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4390 SH_PFC_PIN_GROUP(scif5_data_a),
4391 SH_PFC_PIN_GROUP(scif5_clk_a),
4392 SH_PFC_PIN_GROUP(scif5_data_b),
4393 SH_PFC_PIN_GROUP(scif5_clk_b),
4394 SH_PFC_PIN_GROUP(scif_clk_a),
4395 SH_PFC_PIN_GROUP(scif_clk_b),
4396 SH_PFC_PIN_GROUP(sdhi0_data1),
4397 SH_PFC_PIN_GROUP(sdhi0_data4),
4398 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4399 SH_PFC_PIN_GROUP(sdhi0_cd),
4400 SH_PFC_PIN_GROUP(sdhi0_wp),
4401 SH_PFC_PIN_GROUP(sdhi1_data1),
4402 SH_PFC_PIN_GROUP(sdhi1_data4),
4403 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4404 SH_PFC_PIN_GROUP(sdhi1_cd),
4405 SH_PFC_PIN_GROUP(sdhi1_wp),
4406 SH_PFC_PIN_GROUP(sdhi2_data1),
4407 SH_PFC_PIN_GROUP(sdhi2_data4),
4408 SH_PFC_PIN_GROUP(sdhi2_data8),
4409 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4410 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4411 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4412 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4413 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4414 SH_PFC_PIN_GROUP(sdhi2_ds),
4415 SH_PFC_PIN_GROUP(sdhi3_data1),
4416 SH_PFC_PIN_GROUP(sdhi3_data4),
4417 SH_PFC_PIN_GROUP(sdhi3_data8),
4418 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4419 SH_PFC_PIN_GROUP(sdhi3_cd),
4420 SH_PFC_PIN_GROUP(sdhi3_wp),
4421 SH_PFC_PIN_GROUP(sdhi3_ds),
4422 SH_PFC_PIN_GROUP(ssi0_data),
4423 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4424 SH_PFC_PIN_GROUP(ssi1_data_a),
4425 SH_PFC_PIN_GROUP(ssi1_data_b),
4426 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4427 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4428 SH_PFC_PIN_GROUP(ssi2_data_a),
4429 SH_PFC_PIN_GROUP(ssi2_data_b),
4430 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4431 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4432 SH_PFC_PIN_GROUP(ssi3_data),
4433 SH_PFC_PIN_GROUP(ssi349_ctrl),
4434 SH_PFC_PIN_GROUP(ssi4_data),
4435 SH_PFC_PIN_GROUP(ssi4_ctrl),
4436 SH_PFC_PIN_GROUP(ssi5_data),
4437 SH_PFC_PIN_GROUP(ssi5_ctrl),
4438 SH_PFC_PIN_GROUP(ssi6_data),
4439 SH_PFC_PIN_GROUP(ssi6_ctrl),
4440 SH_PFC_PIN_GROUP(ssi7_data),
4441 SH_PFC_PIN_GROUP(ssi78_ctrl),
4442 SH_PFC_PIN_GROUP(ssi8_data),
4443 SH_PFC_PIN_GROUP(ssi9_data_a),
4444 SH_PFC_PIN_GROUP(ssi9_data_b),
4445 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4446 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4447 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4448 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4449 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4450 SH_PFC_PIN_GROUP(tmu_tclk2_b),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4451 SH_PFC_PIN_GROUP(usb0),
4452 SH_PFC_PIN_GROUP(usb1),
4453 SH_PFC_PIN_GROUP(usb30),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4454 VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4455 VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4456 VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4457 VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4458 SH_PFC_PIN_GROUP(vin4_data18_a),
4459 VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4460 VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4461 VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4462 VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4463 VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4464 VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4465 SH_PFC_PIN_GROUP(vin4_data18_b),
4466 VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4467 VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4468 SH_PFC_PIN_GROUP(vin4_sync),
4469 SH_PFC_PIN_GROUP(vin4_field),
4470 SH_PFC_PIN_GROUP(vin4_clkenb),
4471 SH_PFC_PIN_GROUP(vin4_clk),
4472 SH_PFC_PIN_GROUP(vin5_data8),
4473 SH_PFC_PIN_GROUP(vin5_data10),
4474 SH_PFC_PIN_GROUP(vin5_data12),
4475 SH_PFC_PIN_GROUP(vin5_data16),
4476 SH_PFC_PIN_GROUP(vin5_sync),
4477 SH_PFC_PIN_GROUP(vin5_field),
4478 SH_PFC_PIN_GROUP(vin5_clkenb),
4479 SH_PFC_PIN_GROUP(vin5_clk),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4480};
4481
4482static const char * const audio_clk_groups[] = {
4483 "audio_clk_a_a",
4484 "audio_clk_a_b",
4485 "audio_clk_a_c",
4486 "audio_clk_b_a",
4487 "audio_clk_b_b",
4488 "audio_clk_c_a",
4489 "audio_clk_c_b",
4490 "audio_clkout_a",
4491 "audio_clkout_b",
4492 "audio_clkout_c",
4493 "audio_clkout_d",
4494 "audio_clkout1_a",
4495 "audio_clkout1_b",
4496 "audio_clkout2_a",
4497 "audio_clkout2_b",
4498 "audio_clkout3_a",
4499 "audio_clkout3_b",
4500};
4501
4502static const char * const avb_groups[] = {
4503 "avb_link",
4504 "avb_magic",
4505 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4506 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4507 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4508 "avb_mii",
4509 "avb_avtp_pps",
4510 "avb_avtp_match_a",
4511 "avb_avtp_capture_a",
4512 "avb_avtp_match_b",
4513 "avb_avtp_capture_b",
4514};
4515
4516static const char * const can0_groups[] = {
4517 "can0_data_a",
4518 "can0_data_b",
4519};
4520
4521static const char * const can1_groups[] = {
4522 "can1_data",
4523};
4524
4525static const char * const can_clk_groups[] = {
4526 "can_clk",
4527};
4528
4529static const char * const canfd0_groups[] = {
4530 "canfd0_data_a",
4531 "canfd0_data_b",
4532};
4533
4534static const char * const canfd1_groups[] = {
4535 "canfd1_data",
4536};
4537
4538static const char * const drif0_groups[] = {
4539 "drif0_ctrl_a",
4540 "drif0_data0_a",
4541 "drif0_data1_a",
4542 "drif0_ctrl_b",
4543 "drif0_data0_b",
4544 "drif0_data1_b",
4545 "drif0_ctrl_c",
4546 "drif0_data0_c",
4547 "drif0_data1_c",
4548};
4549
4550static const char * const drif1_groups[] = {
4551 "drif1_ctrl_a",
4552 "drif1_data0_a",
4553 "drif1_data1_a",
4554 "drif1_ctrl_b",
4555 "drif1_data0_b",
4556 "drif1_data1_b",
4557 "drif1_ctrl_c",
4558 "drif1_data0_c",
4559 "drif1_data1_c",
4560};
4561
4562static const char * const drif2_groups[] = {
4563 "drif2_ctrl_a",
4564 "drif2_data0_a",
4565 "drif2_data1_a",
4566 "drif2_ctrl_b",
4567 "drif2_data0_b",
4568 "drif2_data1_b",
4569};
4570
4571static const char * const drif3_groups[] = {
4572 "drif3_ctrl_a",
4573 "drif3_data0_a",
4574 "drif3_data1_a",
4575 "drif3_ctrl_b",
4576 "drif3_data0_b",
4577 "drif3_data1_b",
4578};
4579
4580static const char * const du_groups[] = {
4581 "du_rgb666",
4582 "du_rgb888",
4583 "du_clk_out_0",
4584 "du_clk_out_1",
4585 "du_sync",
4586 "du_oddf",
4587 "du_cde",
4588 "du_disp",
4589};
4590
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]4591static const char * const gp7_02_groups[] = {
4592 "gp7_02",
4593};
4594
4595static const char * const gp7_03_groups[] = {
4596 "gp7_03",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4597};
4598
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4599static const char * const hscif0_groups[] = {
4600 "hscif0_data",
4601 "hscif0_clk",
4602 "hscif0_ctrl",
4603};
4604
4605static const char * const hscif1_groups[] = {
4606 "hscif1_data_a",
4607 "hscif1_clk_a",
4608 "hscif1_ctrl_a",
4609 "hscif1_data_b",
4610 "hscif1_clk_b",
4611 "hscif1_ctrl_b",
4612};
4613
4614static const char * const hscif2_groups[] = {
4615 "hscif2_data_a",
4616 "hscif2_clk_a",
4617 "hscif2_ctrl_a",
4618 "hscif2_data_b",
4619 "hscif2_clk_b",
4620 "hscif2_ctrl_b",
4621 "hscif2_data_c",
4622 "hscif2_clk_c",
4623 "hscif2_ctrl_c",
4624};
4625
4626static const char * const hscif3_groups[] = {
4627 "hscif3_data_a",
4628 "hscif3_clk",
4629 "hscif3_ctrl",
4630 "hscif3_data_b",
4631 "hscif3_data_c",
4632 "hscif3_data_d",
4633};
4634
4635static const char * const hscif4_groups[] = {
4636 "hscif4_data_a",
4637 "hscif4_clk",
4638 "hscif4_ctrl",
4639 "hscif4_data_b",
4640};
4641
4642static const char * const i2c1_groups[] = {
4643 "i2c1_a",
4644 "i2c1_b",
4645};
4646
4647static const char * const i2c2_groups[] = {
4648 "i2c2_a",
4649 "i2c2_b",
4650};
4651
4652static const char * const i2c6_groups[] = {
4653 "i2c6_a",
4654 "i2c6_b",
4655 "i2c6_c",
4656};
4657
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4658static const char * const intc_ex_groups[] = {
4659 "intc_ex_irq0",
4660 "intc_ex_irq1",
4661 "intc_ex_irq2",
4662 "intc_ex_irq3",
4663 "intc_ex_irq4",
4664 "intc_ex_irq5",
4665};
4666
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4667static const char * const msiof0_groups[] = {
4668 "msiof0_clk",
4669 "msiof0_sync",
4670 "msiof0_ss1",
4671 "msiof0_ss2",
4672 "msiof0_txd",
4673 "msiof0_rxd",
4674};
4675
4676static const char * const msiof1_groups[] = {
4677 "msiof1_clk_a",
4678 "msiof1_sync_a",
4679 "msiof1_ss1_a",
4680 "msiof1_ss2_a",
4681 "msiof1_txd_a",
4682 "msiof1_rxd_a",
4683 "msiof1_clk_b",
4684 "msiof1_sync_b",
4685 "msiof1_ss1_b",
4686 "msiof1_ss2_b",
4687 "msiof1_txd_b",
4688 "msiof1_rxd_b",
4689 "msiof1_clk_c",
4690 "msiof1_sync_c",
4691 "msiof1_ss1_c",
4692 "msiof1_ss2_c",
4693 "msiof1_txd_c",
4694 "msiof1_rxd_c",
4695 "msiof1_clk_d",
4696 "msiof1_sync_d",
4697 "msiof1_ss1_d",
4698 "msiof1_ss2_d",
4699 "msiof1_txd_d",
4700 "msiof1_rxd_d",
4701 "msiof1_clk_e",
4702 "msiof1_sync_e",
4703 "msiof1_ss1_e",
4704 "msiof1_ss2_e",
4705 "msiof1_txd_e",
4706 "msiof1_rxd_e",
4707 "msiof1_clk_f",
4708 "msiof1_sync_f",
4709 "msiof1_ss1_f",
4710 "msiof1_ss2_f",
4711 "msiof1_txd_f",
4712 "msiof1_rxd_f",
4713 "msiof1_clk_g",
4714 "msiof1_sync_g",
4715 "msiof1_ss1_g",
4716 "msiof1_ss2_g",
4717 "msiof1_txd_g",
4718 "msiof1_rxd_g",
4719};
4720
4721static const char * const msiof2_groups[] = {
4722 "msiof2_clk_a",
4723 "msiof2_sync_a",
4724 "msiof2_ss1_a",
4725 "msiof2_ss2_a",
4726 "msiof2_txd_a",
4727 "msiof2_rxd_a",
4728 "msiof2_clk_b",
4729 "msiof2_sync_b",
4730 "msiof2_ss1_b",
4731 "msiof2_ss2_b",
4732 "msiof2_txd_b",
4733 "msiof2_rxd_b",
4734 "msiof2_clk_c",
4735 "msiof2_sync_c",
4736 "msiof2_ss1_c",
4737 "msiof2_ss2_c",
4738 "msiof2_txd_c",
4739 "msiof2_rxd_c",
4740 "msiof2_clk_d",
4741 "msiof2_sync_d",
4742 "msiof2_ss1_d",
4743 "msiof2_ss2_d",
4744 "msiof2_txd_d",
4745 "msiof2_rxd_d",
4746};
4747
4748static const char * const msiof3_groups[] = {
4749 "msiof3_clk_a",
4750 "msiof3_sync_a",
4751 "msiof3_ss1_a",
4752 "msiof3_ss2_a",
4753 "msiof3_txd_a",
4754 "msiof3_rxd_a",
4755 "msiof3_clk_b",
4756 "msiof3_sync_b",
4757 "msiof3_ss1_b",
4758 "msiof3_ss2_b",
4759 "msiof3_txd_b",
4760 "msiof3_rxd_b",
4761 "msiof3_clk_c",
4762 "msiof3_sync_c",
4763 "msiof3_txd_c",
4764 "msiof3_rxd_c",
4765 "msiof3_clk_d",
4766 "msiof3_sync_d",
4767 "msiof3_ss1_d",
4768 "msiof3_txd_d",
4769 "msiof3_rxd_d",
4770 "msiof3_clk_e",
4771 "msiof3_sync_e",
4772 "msiof3_ss1_e",
4773 "msiof3_ss2_e",
4774 "msiof3_txd_e",
4775 "msiof3_rxd_e",
4776};
4777
4778static const char * const pwm0_groups[] = {
4779 "pwm0",
4780};
4781
4782static const char * const pwm1_groups[] = {
4783 "pwm1_a",
4784 "pwm1_b",
4785};
4786
4787static const char * const pwm2_groups[] = {
4788 "pwm2_a",
4789 "pwm2_b",
4790};
4791
4792static const char * const pwm3_groups[] = {
4793 "pwm3_a",
4794 "pwm3_b",
4795};
4796
4797static const char * const pwm4_groups[] = {
4798 "pwm4_a",
4799 "pwm4_b",
4800};
4801
4802static const char * const pwm5_groups[] = {
4803 "pwm5_a",
4804 "pwm5_b",
4805};
4806
4807static const char * const pwm6_groups[] = {
4808 "pwm6_a",
4809 "pwm6_b",
4810};
4811
4812static const char * const scif0_groups[] = {
4813 "scif0_data",
4814 "scif0_clk",
4815 "scif0_ctrl",
4816};
4817
4818static const char * const scif1_groups[] = {
4819 "scif1_data_a",
4820 "scif1_clk",
4821 "scif1_ctrl",
4822 "scif1_data_b",
4823};
4824
4825static const char * const scif2_groups[] = {
4826 "scif2_data_a",
4827 "scif2_clk",
4828 "scif2_data_b",
4829};
4830
4831static const char * const scif3_groups[] = {
4832 "scif3_data_a",
4833 "scif3_clk",
4834 "scif3_ctrl",
4835 "scif3_data_b",
4836};
4837
4838static const char * const scif4_groups[] = {
4839 "scif4_data_a",
4840 "scif4_clk_a",
4841 "scif4_ctrl_a",
4842 "scif4_data_b",
4843 "scif4_clk_b",
4844 "scif4_ctrl_b",
4845 "scif4_data_c",
4846 "scif4_clk_c",
4847 "scif4_ctrl_c",
4848};
4849
4850static const char * const scif5_groups[] = {
4851 "scif5_data_a",
4852 "scif5_clk_a",
4853 "scif5_data_b",
4854 "scif5_clk_b",
4855};
4856
4857static const char * const scif_clk_groups[] = {
4858 "scif_clk_a",
4859 "scif_clk_b",
4860};
4861
4862static const char * const sdhi0_groups[] = {
4863 "sdhi0_data1",
4864 "sdhi0_data4",
4865 "sdhi0_ctrl",
4866 "sdhi0_cd",
4867 "sdhi0_wp",
4868};
4869
4870static const char * const sdhi1_groups[] = {
4871 "sdhi1_data1",
4872 "sdhi1_data4",
4873 "sdhi1_ctrl",
4874 "sdhi1_cd",
4875 "sdhi1_wp",
4876};
4877
4878static const char * const sdhi2_groups[] = {
4879 "sdhi2_data1",
4880 "sdhi2_data4",
4881 "sdhi2_data8",
4882 "sdhi2_ctrl",
4883 "sdhi2_cd_a",
4884 "sdhi2_wp_a",
4885 "sdhi2_cd_b",
4886 "sdhi2_wp_b",
4887 "sdhi2_ds",
4888};
4889
4890static const char * const sdhi3_groups[] = {
4891 "sdhi3_data1",
4892 "sdhi3_data4",
4893 "sdhi3_data8",
4894 "sdhi3_ctrl",
4895 "sdhi3_cd",
4896 "sdhi3_wp",
4897 "sdhi3_ds",
4898};
4899
4900static const char * const ssi_groups[] = {
4901 "ssi0_data",
4902 "ssi01239_ctrl",
4903 "ssi1_data_a",
4904 "ssi1_data_b",
4905 "ssi1_ctrl_a",
4906 "ssi1_ctrl_b",
4907 "ssi2_data_a",
4908 "ssi2_data_b",
4909 "ssi2_ctrl_a",
4910 "ssi2_ctrl_b",
4911 "ssi3_data",
4912 "ssi349_ctrl",
4913 "ssi4_data",
4914 "ssi4_ctrl",
4915 "ssi5_data",
4916 "ssi5_ctrl",
4917 "ssi6_data",
4918 "ssi6_ctrl",
4919 "ssi7_data",
4920 "ssi78_ctrl",
4921 "ssi8_data",
4922 "ssi9_data_a",
4923 "ssi9_data_b",
4924 "ssi9_ctrl_a",
4925 "ssi9_ctrl_b",
4926};
4927
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4928static const char * const tmu_groups[] = {
4929 "tmu_tclk1_a",
4930 "tmu_tclk1_b",
4931 "tmu_tclk2_a",
4932 "tmu_tclk2_b",
4933};
4934
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4935static const char * const usb0_groups[] = {
4936 "usb0",
4937};
4938
4939static const char * const usb1_groups[] = {
4940 "usb1",
4941};
4942
4943static const char * const usb30_groups[] = {
4944 "usb30",
4945};
4946
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4947static const char * const vin4_groups[] = {
4948 "vin4_data8_a",
4949 "vin4_data10_a",
4950 "vin4_data12_a",
4951 "vin4_data16_a",
4952 "vin4_data18_a",
4953 "vin4_data20_a",
4954 "vin4_data24_a",
4955 "vin4_data8_b",
4956 "vin4_data10_b",
4957 "vin4_data12_b",
4958 "vin4_data16_b",
4959 "vin4_data18_b",
4960 "vin4_data20_b",
4961 "vin4_data24_b",
4962 "vin4_sync",
4963 "vin4_field",
4964 "vin4_clkenb",
4965 "vin4_clk",
4966};
4967
4968static const char * const vin5_groups[] = {
4969 "vin5_data8",
4970 "vin5_data10",
4971 "vin5_data12",
4972 "vin5_data16",
4973 "vin5_sync",
4974 "vin5_field",
4975 "vin5_clkenb",
4976 "vin5_clk",
4977};
4978
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4979static const struct sh_pfc_function pinmux_functions[] = {
4980 SH_PFC_FUNCTION(audio_clk),
4981 SH_PFC_FUNCTION(avb),
4982 SH_PFC_FUNCTION(can0),
4983 SH_PFC_FUNCTION(can1),
4984 SH_PFC_FUNCTION(can_clk),
4985 SH_PFC_FUNCTION(canfd0),
4986 SH_PFC_FUNCTION(canfd1),
4987 SH_PFC_FUNCTION(drif0),
4988 SH_PFC_FUNCTION(drif1),
4989 SH_PFC_FUNCTION(drif2),
4990 SH_PFC_FUNCTION(drif3),
4991 SH_PFC_FUNCTION(du),
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]4992 SH_PFC_FUNCTION(gp7_02),
4993 SH_PFC_FUNCTION(gp7_03),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4994 SH_PFC_FUNCTION(hscif0),
4995 SH_PFC_FUNCTION(hscif1),
4996 SH_PFC_FUNCTION(hscif2),
4997 SH_PFC_FUNCTION(hscif3),
4998 SH_PFC_FUNCTION(hscif4),
4999 SH_PFC_FUNCTION(i2c1),
5000 SH_PFC_FUNCTION(i2c2),
5001 SH_PFC_FUNCTION(i2c6),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5002 SH_PFC_FUNCTION(intc_ex),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5003 SH_PFC_FUNCTION(msiof0),
5004 SH_PFC_FUNCTION(msiof1),
5005 SH_PFC_FUNCTION(msiof2),
5006 SH_PFC_FUNCTION(msiof3),
5007 SH_PFC_FUNCTION(pwm0),
5008 SH_PFC_FUNCTION(pwm1),
5009 SH_PFC_FUNCTION(pwm2),
5010 SH_PFC_FUNCTION(pwm3),
5011 SH_PFC_FUNCTION(pwm4),
5012 SH_PFC_FUNCTION(pwm5),
5013 SH_PFC_FUNCTION(pwm6),
5014 SH_PFC_FUNCTION(scif0),
5015 SH_PFC_FUNCTION(scif1),
5016 SH_PFC_FUNCTION(scif2),
5017 SH_PFC_FUNCTION(scif3),
5018 SH_PFC_FUNCTION(scif4),
5019 SH_PFC_FUNCTION(scif5),
5020 SH_PFC_FUNCTION(scif_clk),
5021 SH_PFC_FUNCTION(sdhi0),
5022 SH_PFC_FUNCTION(sdhi1),
5023 SH_PFC_FUNCTION(sdhi2),
5024 SH_PFC_FUNCTION(sdhi3),
5025 SH_PFC_FUNCTION(ssi),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5026 SH_PFC_FUNCTION(tmu),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5027 SH_PFC_FUNCTION(usb0),
5028 SH_PFC_FUNCTION(usb1),
5029 SH_PFC_FUNCTION(usb30),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5030 SH_PFC_FUNCTION(vin4),
5031 SH_PFC_FUNCTION(vin5),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5032};
5033
5034static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5035#define F_(x, y) FN_##y
5036#define FM(x) FN_##x
5037 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5038 0, 0,
5039 0, 0,
5040 0, 0,
5041 0, 0,
5042 0, 0,
5043 0, 0,
5044 0, 0,
5045 0, 0,
5046 0, 0,
5047 0, 0,
5048 0, 0,
5049 0, 0,
5050 0, 0,
5051 0, 0,
5052 0, 0,
5053 0, 0,
5054 GP_0_15_FN, GPSR0_15,
5055 GP_0_14_FN, GPSR0_14,
5056 GP_0_13_FN, GPSR0_13,
5057 GP_0_12_FN, GPSR0_12,
5058 GP_0_11_FN, GPSR0_11,
5059 GP_0_10_FN, GPSR0_10,
5060 GP_0_9_FN, GPSR0_9,
5061 GP_0_8_FN, GPSR0_8,
5062 GP_0_7_FN, GPSR0_7,
5063 GP_0_6_FN, GPSR0_6,
5064 GP_0_5_FN, GPSR0_5,
5065 GP_0_4_FN, GPSR0_4,
5066 GP_0_3_FN, GPSR0_3,
5067 GP_0_2_FN, GPSR0_2,
5068 GP_0_1_FN, GPSR0_1,
5069 GP_0_0_FN, GPSR0_0, }
5070 },
5071 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5072 0, 0,
5073 0, 0,
5074 0, 0,
5075 GP_1_28_FN, GPSR1_28,
5076 GP_1_27_FN, GPSR1_27,
5077 GP_1_26_FN, GPSR1_26,
5078 GP_1_25_FN, GPSR1_25,
5079 GP_1_24_FN, GPSR1_24,
5080 GP_1_23_FN, GPSR1_23,
5081 GP_1_22_FN, GPSR1_22,
5082 GP_1_21_FN, GPSR1_21,
5083 GP_1_20_FN, GPSR1_20,
5084 GP_1_19_FN, GPSR1_19,
5085 GP_1_18_FN, GPSR1_18,
5086 GP_1_17_FN, GPSR1_17,
5087 GP_1_16_FN, GPSR1_16,
5088 GP_1_15_FN, GPSR1_15,
5089 GP_1_14_FN, GPSR1_14,
5090 GP_1_13_FN, GPSR1_13,
5091 GP_1_12_FN, GPSR1_12,
5092 GP_1_11_FN, GPSR1_11,
5093 GP_1_10_FN, GPSR1_10,
5094 GP_1_9_FN, GPSR1_9,
5095 GP_1_8_FN, GPSR1_8,
5096 GP_1_7_FN, GPSR1_7,
5097 GP_1_6_FN, GPSR1_6,
5098 GP_1_5_FN, GPSR1_5,
5099 GP_1_4_FN, GPSR1_4,
5100 GP_1_3_FN, GPSR1_3,
5101 GP_1_2_FN, GPSR1_2,
5102 GP_1_1_FN, GPSR1_1,
5103 GP_1_0_FN, GPSR1_0, }
5104 },
5105 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5106 0, 0,
5107 0, 0,
5108 0, 0,
5109 0, 0,
5110 0, 0,
5111 0, 0,
5112 0, 0,
5113 0, 0,
5114 0, 0,
5115 0, 0,
5116 0, 0,
5117 0, 0,
5118 0, 0,
5119 0, 0,
5120 0, 0,
5121 0, 0,
5122 0, 0,
5123 GP_2_14_FN, GPSR2_14,
5124 GP_2_13_FN, GPSR2_13,
5125 GP_2_12_FN, GPSR2_12,
5126 GP_2_11_FN, GPSR2_11,
5127 GP_2_10_FN, GPSR2_10,
5128 GP_2_9_FN, GPSR2_9,
5129 GP_2_8_FN, GPSR2_8,
5130 GP_2_7_FN, GPSR2_7,
5131 GP_2_6_FN, GPSR2_6,
5132 GP_2_5_FN, GPSR2_5,
5133 GP_2_4_FN, GPSR2_4,
5134 GP_2_3_FN, GPSR2_3,
5135 GP_2_2_FN, GPSR2_2,
5136 GP_2_1_FN, GPSR2_1,
5137 GP_2_0_FN, GPSR2_0, }
5138 },
5139 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5140 0, 0,
5141 0, 0,
5142 0, 0,
5143 0, 0,
5144 0, 0,
5145 0, 0,
5146 0, 0,
5147 0, 0,
5148 0, 0,
5149 0, 0,
5150 0, 0,
5151 0, 0,
5152 0, 0,
5153 0, 0,
5154 0, 0,
5155 0, 0,
5156 GP_3_15_FN, GPSR3_15,
5157 GP_3_14_FN, GPSR3_14,
5158 GP_3_13_FN, GPSR3_13,
5159 GP_3_12_FN, GPSR3_12,
5160 GP_3_11_FN, GPSR3_11,
5161 GP_3_10_FN, GPSR3_10,
5162 GP_3_9_FN, GPSR3_9,
5163 GP_3_8_FN, GPSR3_8,
5164 GP_3_7_FN, GPSR3_7,
5165 GP_3_6_FN, GPSR3_6,
5166 GP_3_5_FN, GPSR3_5,
5167 GP_3_4_FN, GPSR3_4,
5168 GP_3_3_FN, GPSR3_3,
5169 GP_3_2_FN, GPSR3_2,
5170 GP_3_1_FN, GPSR3_1,
5171 GP_3_0_FN, GPSR3_0, }
5172 },
5173 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5174 0, 0,
5175 0, 0,
5176 0, 0,
5177 0, 0,
5178 0, 0,
5179 0, 0,
5180 0, 0,
5181 0, 0,
5182 0, 0,
5183 0, 0,
5184 0, 0,
5185 0, 0,
5186 0, 0,
5187 0, 0,
5188 GP_4_17_FN, GPSR4_17,
5189 GP_4_16_FN, GPSR4_16,
5190 GP_4_15_FN, GPSR4_15,
5191 GP_4_14_FN, GPSR4_14,
5192 GP_4_13_FN, GPSR4_13,
5193 GP_4_12_FN, GPSR4_12,
5194 GP_4_11_FN, GPSR4_11,
5195 GP_4_10_FN, GPSR4_10,
5196 GP_4_9_FN, GPSR4_9,
5197 GP_4_8_FN, GPSR4_8,
5198 GP_4_7_FN, GPSR4_7,
5199 GP_4_6_FN, GPSR4_6,
5200 GP_4_5_FN, GPSR4_5,
5201 GP_4_4_FN, GPSR4_4,
5202 GP_4_3_FN, GPSR4_3,
5203 GP_4_2_FN, GPSR4_2,
5204 GP_4_1_FN, GPSR4_1,
5205 GP_4_0_FN, GPSR4_0, }
5206 },
5207 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5208 0, 0,
5209 0, 0,
5210 0, 0,
5211 0, 0,
5212 0, 0,
5213 0, 0,
5214 GP_5_25_FN, GPSR5_25,
5215 GP_5_24_FN, GPSR5_24,
5216 GP_5_23_FN, GPSR5_23,
5217 GP_5_22_FN, GPSR5_22,
5218 GP_5_21_FN, GPSR5_21,
5219 GP_5_20_FN, GPSR5_20,
5220 GP_5_19_FN, GPSR5_19,
5221 GP_5_18_FN, GPSR5_18,
5222 GP_5_17_FN, GPSR5_17,
5223 GP_5_16_FN, GPSR5_16,
5224 GP_5_15_FN, GPSR5_15,
5225 GP_5_14_FN, GPSR5_14,
5226 GP_5_13_FN, GPSR5_13,
5227 GP_5_12_FN, GPSR5_12,
5228 GP_5_11_FN, GPSR5_11,
5229 GP_5_10_FN, GPSR5_10,
5230 GP_5_9_FN, GPSR5_9,
5231 GP_5_8_FN, GPSR5_8,
5232 GP_5_7_FN, GPSR5_7,
5233 GP_5_6_FN, GPSR5_6,
5234 GP_5_5_FN, GPSR5_5,
5235 GP_5_4_FN, GPSR5_4,
5236 GP_5_3_FN, GPSR5_3,
5237 GP_5_2_FN, GPSR5_2,
5238 GP_5_1_FN, GPSR5_1,
5239 GP_5_0_FN, GPSR5_0, }
5240 },
5241 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5242 GP_6_31_FN, GPSR6_31,
5243 GP_6_30_FN, GPSR6_30,
5244 GP_6_29_FN, GPSR6_29,
5245 GP_6_28_FN, GPSR6_28,
5246 GP_6_27_FN, GPSR6_27,
5247 GP_6_26_FN, GPSR6_26,
5248 GP_6_25_FN, GPSR6_25,
5249 GP_6_24_FN, GPSR6_24,
5250 GP_6_23_FN, GPSR6_23,
5251 GP_6_22_FN, GPSR6_22,
5252 GP_6_21_FN, GPSR6_21,
5253 GP_6_20_FN, GPSR6_20,
5254 GP_6_19_FN, GPSR6_19,
5255 GP_6_18_FN, GPSR6_18,
5256 GP_6_17_FN, GPSR6_17,
5257 GP_6_16_FN, GPSR6_16,
5258 GP_6_15_FN, GPSR6_15,
5259 GP_6_14_FN, GPSR6_14,
5260 GP_6_13_FN, GPSR6_13,
5261 GP_6_12_FN, GPSR6_12,
5262 GP_6_11_FN, GPSR6_11,
5263 GP_6_10_FN, GPSR6_10,
5264 GP_6_9_FN, GPSR6_9,
5265 GP_6_8_FN, GPSR6_8,
5266 GP_6_7_FN, GPSR6_7,
5267 GP_6_6_FN, GPSR6_6,
5268 GP_6_5_FN, GPSR6_5,
5269 GP_6_4_FN, GPSR6_4,
5270 GP_6_3_FN, GPSR6_3,
5271 GP_6_2_FN, GPSR6_2,
5272 GP_6_1_FN, GPSR6_1,
5273 GP_6_0_FN, GPSR6_0, }
5274 },
5275 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5276 0, 0,
5277 0, 0,
5278 0, 0,
5279 0, 0,
5280 0, 0,
5281 0, 0,
5282 0, 0,
5283 0, 0,
5284 0, 0,
5285 0, 0,
5286 0, 0,
5287 0, 0,
5288 0, 0,
5289 0, 0,
5290 0, 0,
5291 0, 0,
5292 0, 0,
5293 0, 0,
5294 0, 0,
5295 0, 0,
5296 0, 0,
5297 0, 0,
5298 0, 0,
5299 0, 0,
5300 0, 0,
5301 0, 0,
5302 0, 0,
5303 0, 0,
5304 GP_7_3_FN, GPSR7_3,
5305 GP_7_2_FN, GPSR7_2,
5306 GP_7_1_FN, GPSR7_1,
5307 GP_7_0_FN, GPSR7_0, }
5308 },
5309#undef F_
5310#undef FM
5311
5312#define F_(x, y) x,
5313#define FM(x) FN_##x,
5314 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5315 IP0_31_28
5316 IP0_27_24
5317 IP0_23_20
5318 IP0_19_16
5319 IP0_15_12
5320 IP0_11_8
5321 IP0_7_4
5322 IP0_3_0 }
5323 },
5324 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5325 IP1_31_28
5326 IP1_27_24
5327 IP1_23_20
5328 IP1_19_16
5329 IP1_15_12
5330 IP1_11_8
5331 IP1_7_4
5332 IP1_3_0 }
5333 },
5334 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5335 IP2_31_28
5336 IP2_27_24
5337 IP2_23_20
5338 IP2_19_16
5339 IP2_15_12
5340 IP2_11_8
5341 IP2_7_4
5342 IP2_3_0 }
5343 },
5344 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5345 IP3_31_28
5346 IP3_27_24
5347 IP3_23_20
5348 IP3_19_16
5349 IP3_15_12
5350 IP3_11_8
5351 IP3_7_4
5352 IP3_3_0 }
5353 },
5354 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5355 IP4_31_28
5356 IP4_27_24
5357 IP4_23_20
5358 IP4_19_16
5359 IP4_15_12
5360 IP4_11_8
5361 IP4_7_4
5362 IP4_3_0 }
5363 },
5364 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5365 IP5_31_28
5366 IP5_27_24
5367 IP5_23_20
5368 IP5_19_16
5369 IP5_15_12
5370 IP5_11_8
5371 IP5_7_4
5372 IP5_3_0 }
5373 },
5374 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5375 IP6_31_28
5376 IP6_27_24
5377 IP6_23_20
5378 IP6_19_16
5379 IP6_15_12
5380 IP6_11_8
5381 IP6_7_4
5382 IP6_3_0 }
5383 },
5384 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5385 IP7_31_28
5386 IP7_27_24
5387 IP7_23_20
5388 IP7_19_16
5389 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5390 IP7_11_8
5391 IP7_7_4
5392 IP7_3_0 }
5393 },
5394 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5395 IP8_31_28
5396 IP8_27_24
5397 IP8_23_20
5398 IP8_19_16
5399 IP8_15_12
5400 IP8_11_8
5401 IP8_7_4
5402 IP8_3_0 }
5403 },
5404 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5405 IP9_31_28
5406 IP9_27_24
5407 IP9_23_20
5408 IP9_19_16
5409 IP9_15_12
5410 IP9_11_8
5411 IP9_7_4
5412 IP9_3_0 }
5413 },
5414 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5415 IP10_31_28
5416 IP10_27_24
5417 IP10_23_20
5418 IP10_19_16
5419 IP10_15_12
5420 IP10_11_8
5421 IP10_7_4
5422 IP10_3_0 }
5423 },
5424 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5425 IP11_31_28
5426 IP11_27_24
5427 IP11_23_20
5428 IP11_19_16
5429 IP11_15_12
5430 IP11_11_8
5431 IP11_7_4
5432 IP11_3_0 }
5433 },
5434 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5435 IP12_31_28
5436 IP12_27_24
5437 IP12_23_20
5438 IP12_19_16
5439 IP12_15_12
5440 IP12_11_8
5441 IP12_7_4
5442 IP12_3_0 }
5443 },
5444 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5445 IP13_31_28
5446 IP13_27_24
5447 IP13_23_20
5448 IP13_19_16
5449 IP13_15_12
5450 IP13_11_8
5451 IP13_7_4
5452 IP13_3_0 }
5453 },
5454 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5455 IP14_31_28
5456 IP14_27_24
5457 IP14_23_20
5458 IP14_19_16
5459 IP14_15_12
5460 IP14_11_8
5461 IP14_7_4
5462 IP14_3_0 }
5463 },
5464 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5465 IP15_31_28
5466 IP15_27_24
5467 IP15_23_20
5468 IP15_19_16
5469 IP15_15_12
5470 IP15_11_8
5471 IP15_7_4
5472 IP15_3_0 }
5473 },
5474 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5475 IP16_31_28
5476 IP16_27_24
5477 IP16_23_20
5478 IP16_19_16
5479 IP16_15_12
5480 IP16_11_8
5481 IP16_7_4
5482 IP16_3_0 }
5483 },
5484 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5485 IP17_31_28
5486 IP17_27_24
5487 IP17_23_20
5488 IP17_19_16
5489 IP17_15_12
5490 IP17_11_8
5491 IP17_7_4
5492 IP17_3_0 }
5493 },
5494 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5495 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5496 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5497 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5498 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5499 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5500 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5501 IP18_7_4
5502 IP18_3_0 }
5503 },
5504#undef F_
5505#undef FM
5506
5507#define F_(x, y) x,
5508#define FM(x) FN_##x,
5509 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5510 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5511 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5512 MOD_SEL0_31_30_29
5513 MOD_SEL0_28_27
5514 MOD_SEL0_26_25_24
5515 MOD_SEL0_23
5516 MOD_SEL0_22
5517 MOD_SEL0_21
5518 MOD_SEL0_20
5519 MOD_SEL0_19
5520 MOD_SEL0_18_17
5521 MOD_SEL0_16
5522 0, 0, /* RESERVED 15 */
5523 MOD_SEL0_14_13
5524 MOD_SEL0_12
5525 MOD_SEL0_11
5526 MOD_SEL0_10
5527 MOD_SEL0_9_8
5528 MOD_SEL0_7_6
5529 MOD_SEL0_5
5530 MOD_SEL0_4_3
5531 /* RESERVED 2, 1, 0 */
5532 0, 0, 0, 0, 0, 0, 0, 0 }
5533 },
5534 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5535 2, 3, 1, 2, 3, 1, 1, 2, 1,
5536 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5537 MOD_SEL1_31_30
5538 MOD_SEL1_29_28_27
5539 MOD_SEL1_26
5540 MOD_SEL1_25_24
5541 MOD_SEL1_23_22_21
5542 MOD_SEL1_20
5543 MOD_SEL1_19
5544 MOD_SEL1_18_17
5545 MOD_SEL1_16
5546 MOD_SEL1_15_14
5547 MOD_SEL1_13
5548 MOD_SEL1_12
5549 MOD_SEL1_11
5550 MOD_SEL1_10
5551 MOD_SEL1_9
5552 0, 0, 0, 0, /* RESERVED 8, 7 */
5553 MOD_SEL1_6
5554 MOD_SEL1_5
5555 MOD_SEL1_4
5556 MOD_SEL1_3
5557 MOD_SEL1_2
5558 MOD_SEL1_1
5559 MOD_SEL1_0 }
5560 },
5561 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5562 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5563 4, 4, 4, 3, 1) {
5564 MOD_SEL2_31
5565 MOD_SEL2_30
5566 MOD_SEL2_29
5567 MOD_SEL2_28_27
5568 MOD_SEL2_26
5569 MOD_SEL2_25_24_23
5570 MOD_SEL2_22
5571 MOD_SEL2_21
5572 MOD_SEL2_20
5573 MOD_SEL2_19
5574 MOD_SEL2_18
5575 MOD_SEL2_17
5576 /* RESERVED 16 */
5577 0, 0,
5578 /* RESERVED 15, 14, 13, 12 */
5579 0, 0, 0, 0, 0, 0, 0, 0,
5580 0, 0, 0, 0, 0, 0, 0, 0,
5581 /* RESERVED 11, 10, 9, 8 */
5582 0, 0, 0, 0, 0, 0, 0, 0,
5583 0, 0, 0, 0, 0, 0, 0, 0,
5584 /* RESERVED 7, 6, 5, 4 */
5585 0, 0, 0, 0, 0, 0, 0, 0,
5586 0, 0, 0, 0, 0, 0, 0, 0,
5587 /* RESERVED 3, 2, 1 */
5588 0, 0, 0, 0, 0, 0, 0, 0,
5589 MOD_SEL2_0 }
5590 },
5591 { },
5592};
5593
5594static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5595 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5596 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5597 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5598 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5599 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5600 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5601 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5602 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5603 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5604 } },
5605 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5606 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5607 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5608 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5609 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5610 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5611 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5612 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5613 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5614 } },
5615 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5616 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5617 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5618 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5619 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5620 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5621 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5622 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5623 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5624 } },
5625 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5626 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5627 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5628 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5629 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5630 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5631 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5632 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5633 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5634 } },
5635 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5636 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5637 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5638 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5639 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5640 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5641 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5642 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5643 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5644 } },
5645 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5646 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5647 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5648 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5649 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5650 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5651 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5652 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5653 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5654 } },
5655 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5656 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5657 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5658 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5659 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5660 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5661 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5662 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5663 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5664 } },
5665 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5666 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5667 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5668 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5669 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5670 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5671 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5672 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5673 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5674 } },
5675 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5676 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5677 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5678 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5679 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5680 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5681 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5682 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5683 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5684 } },
5685 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5686 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5687 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5688 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5689 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5690 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5691 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5692 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5693 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5694 } },
5695 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5696 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5697 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5698 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5699 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5700 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5701 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5702 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5703 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5704 } },
5705 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5706 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5707 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5708 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5709 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]5710 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5711 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5712 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5713 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5714 } },
5715 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5716 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5717 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5718 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5719 } },
5720 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5721 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5722 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5723 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5724 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5725 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5726 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5727 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5728 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5729 } },
5730 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5731 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5732 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5733 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5734 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5735 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5736 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5737 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5738 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5739 } },
5740 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5741 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5742 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5743 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5744 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5745 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5746 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5747 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5748 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5749 } },
5750 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5751 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5752 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5753 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5754 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5755 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5756 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5757 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5758 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5759 } },
5760 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5761 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5762 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5763 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5764 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5765 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5766 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5767 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5768 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5769 } },
5770 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5771 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5772 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5773 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5774 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5775 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5776 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5777 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5778 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5779 } },
5780 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5781 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5782 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5783 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5784 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5785 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5786 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5787 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5788 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5789 } },
5790 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5791 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5792 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5793 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5794 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5795 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5796 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5797 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5798 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5799 } },
5800 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5801 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5802 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5803 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5804 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5805 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5806 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5807 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5808 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5809 } },
5810 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5811 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5812 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5813 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5814 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5815 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5816 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5817 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5818 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5819 } },
5820 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5821 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5822 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5823 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5824 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5825 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5826 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5827 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5828 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5829 } },
5830 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5831 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5832 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5833 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5834 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5835 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5836 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5837 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5838 } },
5839 { },
5840};
5841
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5842enum ioctrl_regs {
5843 POCCTRL,
5844};
5845
5846static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5847 [POCCTRL] = { 0xe6060380, },
5848 { /* sentinel */ },
5849};
5850
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5851static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5852{
5853 int bit = -EINVAL;
5854
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5855 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5856
5857 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5858 bit = pin & 0x1f;
5859
5860 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5861 bit = (pin & 0x1f) + 12;
5862
5863 return bit;
5864}
5865
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5866static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5867 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5868 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5869 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5870 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5871 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5872 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5873 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5874 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5875 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5876 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5877 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5878 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5879 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5880 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5881 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5882 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5883 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5884 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5885 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5886 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5887 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5888 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5889 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5890 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5891 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5892 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5893 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5894 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5895 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5896 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5897 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5898 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5899 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5900 } },
5901 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5902 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5903 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5904 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5905 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5906 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5907 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5908 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5909 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5910 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5911 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5912 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5913 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5914 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5915 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5916 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5917 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5918 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5919 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5920 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5921 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5922 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5923 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5924 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5925 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5926 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5927 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5928 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5929 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5930 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5931 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5932 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5933 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5934 } },
5935 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5936 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5937 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5938 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5939 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5940 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5941 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5942 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5943 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5944 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5945 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5946 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5947 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5948 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5949 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5950 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5951 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5952 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5953 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5954 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5955 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5956 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5957 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5958 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5959 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5960 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5961 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5962 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5963 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Hiroyuki Yokoyamaf4059dc2019-02-12 19:09:13 +0900[diff] [blame]5964 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5965 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5966 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5967 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5968 } },
5969 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5970 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5971 [ 1] = PIN_NONE,
5972 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5973 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5974 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5975 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5976 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5977 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5978 [ 8] = PIN_NONE,
5979 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5980 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5981 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5982 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5983 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5984 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5985 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5986 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5987 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5988 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5989 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5990 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5991 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5992 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5993 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5994 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5995 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5996 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5997 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5998 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5999 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6000 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6001 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6002 } },
6003 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6004 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6005 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6006 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6007 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6008 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6009 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6010 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6011 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6012 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6013 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6014 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6015 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6016 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6017 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6018 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6019 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6020 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6021 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6022 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6023 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6024 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6025 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6026 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6027 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6028 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6029 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6030 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6031 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6032 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6033 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6034 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6035 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6036 } },
6037 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6038 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6039 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6040 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6041 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6042 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6043 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6044 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6045 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6046 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6047 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6048 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6049 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6050 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6051 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6052 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6053 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6054 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6055 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6056 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6057 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6058 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6059 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6060 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6061 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6062 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6063 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6064 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6065 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6066 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6067 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6068 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6069 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6070 } },
6071 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6072 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6073 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6074 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6075 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6076 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6077 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6078 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6079 [ 7] = PIN_NONE,
6080 [ 8] = PIN_NONE,
6081 [ 9] = PIN_NONE,
6082 [10] = PIN_NONE,
6083 [11] = PIN_NONE,
6084 [12] = PIN_NONE,
6085 [13] = PIN_NONE,
6086 [14] = PIN_NONE,
6087 [15] = PIN_NONE,
6088 [16] = PIN_NONE,
6089 [17] = PIN_NONE,
6090 [18] = PIN_NONE,
6091 [19] = PIN_NONE,
6092 [20] = PIN_NONE,
6093 [21] = PIN_NONE,
6094 [22] = PIN_NONE,
6095 [23] = PIN_NONE,
6096 [24] = PIN_NONE,
6097 [25] = PIN_NONE,
6098 [26] = PIN_NONE,
6099 [27] = PIN_NONE,
6100 [28] = PIN_NONE,
6101 [29] = PIN_NONE,
6102 [30] = PIN_NONE,
6103 [31] = PIN_NONE,
6104 } },
6105 { /* sentinel */ },
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6106};
6107
6108static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6109 unsigned int pin)
6110{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6111 const struct pinmux_bias_reg *reg;
6112 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6113
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6114 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6115 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6116 return PIN_CONFIG_BIAS_DISABLE;
6117
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6118 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6119 return PIN_CONFIG_BIAS_DISABLE;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6120 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6121 return PIN_CONFIG_BIAS_PULL_UP;
6122 else
6123 return PIN_CONFIG_BIAS_PULL_DOWN;
6124}
6125
6126static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6127 unsigned int bias)
6128{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6129 const struct pinmux_bias_reg *reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6130 u32 enable, updown;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6131 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6132
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6133 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6134 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6135 return;
6136
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6137 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6138 if (bias != PIN_CONFIG_BIAS_DISABLE)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6139 enable |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6140
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6141 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6142 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6143 updown |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6144
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6145 sh_pfc_write(pfc, reg->pud, updown);
6146 sh_pfc_write(pfc, reg->puen, enable);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6147}
6148
6149static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6150 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6151 .get_bias = r8a7796_pinmux_get_bias,
6152 .set_bias = r8a7796_pinmux_set_bias,
6153};
6154
6155const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6156 .name = "r8a77960_pfc",
6157 .ops = &r8a7796_pinmux_ops,
6158 .unlock_reg = 0xe6060000, /* PMMR */
6159
6160 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6161
6162 .pins = pinmux_pins,
6163 .nr_pins = ARRAY_SIZE(pinmux_pins),
6164 .groups = pinmux_groups,
6165 .nr_groups = ARRAY_SIZE(pinmux_groups),
6166 .functions = pinmux_functions,
6167 .nr_functions = ARRAY_SIZE(pinmux_functions),
6168
6169 .cfg_regs = pinmux_config_regs,
6170 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6171 .bias_regs = pinmux_bias_regs,
6172 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6173
6174 .pinmux_data = pinmux_data,
6175 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6176};