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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hud2396512016-09-07 18:47:28 +08002/*
3 * Copyright 2016 Freescale Semiconductor
Yangbo Lubb32e682021-06-03 10:51:19 +08004 * Copyright 2019-2021 NXP
Mingkai Hud2396512016-09-07 18:47:28 +08005 */
6
7#ifndef __LS1046A_COMMON_H
8#define __LS1046A_COMMON_H
9
Sumit Gargc064fc72017-03-30 09:53:13 +053010/* SPL build */
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_QBMAN
13#define SPL_NO_FMAN
14#define SPL_NO_ENV
15#define SPL_NO_MISC
16#define SPL_NO_QSPI
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#endif
York Sun3e512d82018-06-26 14:48:29 -070020#if defined(CONFIG_SPL_BUILD) && \
21 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
Sumit Gargc064fc72017-03-30 09:53:13 +053022#define SPL_NO_MMC
23#endif
York Sunc5c8e1e2018-06-08 16:37:27 -070024#if defined(CONFIG_SPL_BUILD) && \
York Sunc5c8e1e2018-06-08 16:37:27 -070025 !defined(CONFIG_SPL_FSL_LS_PPA)
Sumit Gargc064fc72017-03-30 09:53:13 +053026#define SPL_NO_IFC
27#endif
28
Mingkai Hud2396512016-09-07 18:47:28 +080029#define CONFIG_REMAKE_ELF
Mingkai Hud2396512016-09-07 18:47:28 +080030
31#include <asm/arch/config.h>
Bharat Bhushanc882dd72017-03-22 12:06:28 +053032#include <asm/arch/stream_id_lsch2.h>
Mingkai Hud2396512016-09-07 18:47:28 +080033
34/* Link Definitions */
Rajesh Bhagatcb6153b2018-11-05 18:02:36 +000035#ifdef CONFIG_TFABOOT
36#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
37#else
Mingkai Hud2396512016-09-07 18:47:28 +080038#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Rajesh Bhagatcb6153b2018-11-05 18:02:36 +000039#endif
Mingkai Hud2396512016-09-07 18:47:28 +080040
Mingkai Hud2396512016-09-07 18:47:28 +080041#define CONFIG_VERY_BIG_RAM
42#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
43#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
44#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
45#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
46
Michael Wallef056e0f2020-06-01 21:53:26 +020047#define CPU_RELEASE_ADDR secondary_boot_addr
Mingkai Hud2396512016-09-07 18:47:28 +080048
49/* Generic Timer Definitions */
50#define COUNTER_FREQUENCY 25000000 /* 25MHz */
51
Mingkai Hud2396512016-09-07 18:47:28 +080052/* Serial Port */
Mingkai Hud2396512016-09-07 18:47:28 +080053#define CONFIG_SYS_NS16550_SERIAL
54#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +080055#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Hud2396512016-09-07 18:47:28 +080056
Mingkai Hud2396512016-09-07 18:47:28 +080057/* SD boot SPL */
58#ifdef CONFIG_SD_BOOT
Mingkai Hud2396512016-09-07 18:47:28 +080059#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
60#define CONFIG_SPL_STACK 0x10020000
61#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
62#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
63#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
64#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
65 CONFIG_SPL_BSS_MAX_SIZE)
66#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
Ruchika Gupta0009c8f2017-04-17 18:07:19 +053067
Udit Agarwal22ec2382019-11-07 16:11:32 +000068#ifdef CONFIG_NXP_ESBC
Ruchika Gupta0009c8f2017-04-17 18:07:19 +053069#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
70/*
71 * HDR would be appended at end of image and copied to DDR along
72 * with U-Boot image. Here u-boot max. size is 512K. So if binary
73 * size increases then increase this size in case of secure boot as
74 * it uses raw u-boot image instead of fit image.
75 */
76#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
77#else
78#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal22ec2382019-11-07 16:11:32 +000079#endif /* ifdef CONFIG_NXP_ESBC */
Mingkai Hud2396512016-09-07 18:47:28 +080080#endif
81
York Sun3e512d82018-06-26 14:48:29 -070082#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
83#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
York Sun3e512d82018-06-26 14:48:29 -070084#define CONFIG_SPL_MAX_SIZE 0x1f000
85#define CONFIG_SPL_STACK 0x10020000
86#define CONFIG_SPL_PAD_TO 0x20000
87#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
88#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
89#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
90 CONFIG_SPL_BSS_MAX_SIZE)
91#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
92#define CONFIG_SYS_MONITOR_LEN 0x100000
York Sun3e512d82018-06-26 14:48:29 -070093#endif
94
Shaohui Xie085ac1c2016-09-07 17:56:14 +080095/* NAND SPL */
96#ifdef CONFIG_NAND_BOOT
97#define CONFIG_SPL_PBL_PAD
Shaohui Xie085ac1c2016-09-07 17:56:14 +080098
Ruchika Gupta0009c8f2017-04-17 18:07:19 +053099#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800100#define CONFIG_SPL_STACK 0x1001f000
101#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
102#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
103
104#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
105#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
106#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
107 CONFIG_SPL_BSS_MAX_SIZE)
108#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
109#define CONFIG_SYS_MONITOR_LEN 0xa0000
110#endif
111
Biwen Li479b9bd2021-02-05 19:02:01 +0800112/* GPIO */
113#ifdef CONFIG_DM_GPIO
114#ifndef CONFIG_MPC8XXX_GPIO
115#define CONFIG_MPC8XXX_GPIO
116#endif
117#endif
118
Mingkai Hud2396512016-09-07 18:47:28 +0800119/* I2C */
Mingkai Hud2396512016-09-07 18:47:28 +0800120
Hou Zhiqiang105457e2017-04-14 16:49:01 +0800121/* PCIe */
122#define CONFIG_PCIE1 /* PCIE controller 1 */
123#define CONFIG_PCIE2 /* PCIE controller 2 */
124#define CONFIG_PCIE3 /* PCIE controller 3 */
125
126#ifdef CONFIG_PCI
127#define CONFIG_PCI_SCAN_SHOW
Hou Zhiqiang105457e2017-04-14 16:49:01 +0800128#endif
129
Yuantian Tangd24716d2018-01-03 15:53:09 +0800130/* SATA */
131#ifndef SPL_NO_SATA
132#define CONFIG_SCSI_AHCI_PLAT
133
134#define CONFIG_SYS_SATA AHCI_BASE_ADDR
135
136#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
137#define CONFIG_SYS_SCSI_MAX_LUN 1
138#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
139 CONFIG_SYS_SCSI_MAX_LUN)
140#endif
141
Mingkai Hud2396512016-09-07 18:47:28 +0800142/* FMan ucode */
Sumit Gargc064fc72017-03-30 09:53:13 +0530143#ifndef SPL_NO_FMAN
Mingkai Hud2396512016-09-07 18:47:28 +0800144#define CONFIG_SYS_DPAA_FMAN
145#ifdef CONFIG_SYS_DPAA_FMAN
146#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
Sumit Gargc064fc72017-03-30 09:53:13 +0530147#endif
Mingkai Hud2396512016-09-07 18:47:28 +0800148#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
149#endif
150
151/* Miscellaneous configurable options */
Mingkai Hud2396512016-09-07 18:47:28 +0800152
153#define CONFIG_HWCONFIG
154#define HWCONFIG_BUFFER_SIZE 128
155
Qianyu Gong6264ab62017-06-15 11:10:09 +0800156#ifndef CONFIG_SPL_BUILD
157#define BOOT_TARGET_DEVICES(func) \
Yuantian Tangd24716d2018-01-03 15:53:09 +0800158 func(SCSI, scsi, 0) \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800159 func(MMC, mmc, 0) \
Mian Yousaf Kaukabe1721582019-01-29 16:38:37 +0100160 func(USB, usb, 0) \
161 func(DHCP, dhcp, na)
Qianyu Gong6264ab62017-06-15 11:10:09 +0800162#include <config_distro_bootcmd.h>
163#endif
164
Vabhav Sharma51641912019-06-06 12:35:28 +0000165#if defined(CONFIG_TARGET_LS1046AFRWY)
166#define LS1046A_BOOT_SRC_AND_HDR\
167 "boot_scripts=ls1046afrwy_boot.scr\0" \
168 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
Biwen Li88dd2e82020-04-20 18:29:06 +0800169#elif defined(CONFIG_TARGET_LS1046AQDS)
170#define LS1046A_BOOT_SRC_AND_HDR\
171 "boot_scripts=ls1046aqds_boot.scr\0" \
172 "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
Vabhav Sharma51641912019-06-06 12:35:28 +0000173#else
174#define LS1046A_BOOT_SRC_AND_HDR\
175 "boot_scripts=ls1046ardb_boot.scr\0" \
176 "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
177#endif
Sumit Gargc064fc72017-03-30 09:53:13 +0530178#ifndef SPL_NO_MISC
Mingkai Hud2396512016-09-07 18:47:28 +0800179/* Initial environment variables */
180#define CONFIG_EXTRA_ENV_SETTINGS \
181 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800182 "ramdisk_addr=0x800000\0" \
183 "ramdisk_size=0x2000000\0" \
Yuantian Tange1786d32020-02-19 17:02:22 +0800184 "bootm_size=0x10000000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800185 "fdt_addr=0x64f00000\0" \
Biwen Li88dd2e82020-04-20 18:29:06 +0800186 "kernel_addr=0x61000000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800187 "scriptaddr=0x80000000\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530188 "scripthdraddr=0x80080000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800189 "fdtheader_addr_r=0x80100000\0" \
190 "kernelheader_addr_r=0x80200000\0" \
191 "load_addr=0xa0000000\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530192 "kernel_addr_r=0x81000000\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800193 "fdt_addr_r=0x90000000\0" \
194 "ramdisk_addr_r=0xa0000000\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800195 "kernel_start=0x1000000\0" \
Priyanka Singha83b8db2020-01-22 10:29:46 +0000196 "kernelheader_start=0x600000\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800197 "kernel_load=0xa0000000\0" \
198 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530199 "kernelheader_size=0x40000\0" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800200 "kernel_addr_sd=0x8000\0" \
201 "kernel_size_sd=0x14000\0" \
Priyanka Singha83b8db2020-01-22 10:29:46 +0000202 "kernelhdr_addr_sd=0x3000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530203 "kernelhdr_size_sd=0x10\0" \
Mingkai Hud2396512016-09-07 18:47:28 +0800204 "console=ttyS0,115200\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400205 CONFIG_MTDPARTS_DEFAULT "\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800206 BOOTENV \
Vabhav Sharma51641912019-06-06 12:35:28 +0000207 LS1046A_BOOT_SRC_AND_HDR \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800208 "scan_dev_for_boot_part=" \
209 "part list ${devtype} ${devnum} devplist; " \
210 "env exists devplist || setenv devplist 1; " \
211 "for distro_bootpart in ${devplist}; do " \
212 "if fstype ${devtype} " \
213 "${devnum}:${distro_bootpart} " \
214 "bootfstype; then " \
215 "run scan_dev_for_boot; " \
216 "fi; " \
217 "done\0" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530218 "boot_a_script=" \
219 "load ${devtype} ${devnum}:${distro_bootpart} " \
220 "${scriptaddr} ${prefix}${script}; " \
221 "env exists secureboot && load ${devtype} " \
222 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai25355ec2019-04-23 05:52:17 +0000223 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
224 "env exists secureboot " \
225 "&& esbc_validate ${scripthdraddr};" \
Sumit Garg860a3bd2017-06-06 20:50:29 +0530226 "source ${scriptaddr}\0" \
Qianyu Gong6264ab62017-06-15 11:10:09 +0800227 "qspi_bootcmd=echo Trying load from qspi..;" \
228 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530229 "$kernel_start $kernel_size; env exists secureboot " \
230 "&& sf read $kernelheader_addr_r $kernelheader_start " \
231 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
232 "bootm $load_addr#$board\0" \
Biwen Li88dd2e82020-04-20 18:29:06 +0800233 "nand_bootcmd=echo Trying load from nand..;" \
234 "nand info; nand read $load_addr " \
235 "$kernel_start $kernel_size; env exists secureboot " \
236 "&& nand read $kernelheader_addr_r $kernelheader_start " \
237 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
238 "bootm $load_addr#$board\0" \
239 "nor_bootcmd=echo Trying load from nor..;" \
240 "cp.b $kernel_addr $load_addr " \
241 "$kernel_size; env exists secureboot " \
242 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
243 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
244 "bootm $load_addr#$board\0" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800245 "sd_bootcmd=echo Trying load from SD ..;" \
246 "mmcinfo; mmc read $load_addr " \
247 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530248 "env exists secureboot && mmc read $kernelheader_addr_r " \
249 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
250 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu47e7e032017-11-09 17:57:56 +0800251 "bootm $load_addr#$board\0"
Qianyu Gong6264ab62017-06-15 11:10:09 +0800252
Sumit Gargc064fc72017-03-30 09:53:13 +0530253#endif
254
Mingkai Hud2396512016-09-07 18:47:28 +0800255/* Monitor Command Prompt */
256#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sumit Gargc064fc72017-03-30 09:53:13 +0530257
Mingkai Hud2396512016-09-07 18:47:28 +0800258#define CONFIG_SYS_MAXARGS 64 /* max command args */
259
260#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
261
Simon Glass89e0a3a2017-05-17 08:23:10 -0600262#include <asm/arch/soc.h>
263
Mingkai Hud2396512016-09-07 18:47:28 +0800264#endif /* __LS1046A_COMMON_H */