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wdenkb98ac282004-02-24 00:16:43 +00001/*
2 * Startup Code for S3C44B0 CPU-core
3 *
4 * (C) Copyright 2004
5 * DAVE Srl
6 *
7 * http://www.dave-tech.it
8 * http://www.wawnet.biz
9 * mailto:info@wawnet.biz
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
Wolfgang Denk0191e472010-10-26 14:34:52 +020030#include <asm-offsets.h>
wdenkb98ac282004-02-24 00:16:43 +000031#include <config.h>
32#include <version.h>
33
wdenkb98ac282004-02-24 00:16:43 +000034/*
35 * Jump vector table
36 */
37
38
39.globl _start
40_start: b reset
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
48
49 .balignl 16,0xdeadbeef
50
51
52/*
53 *************************************************************************
54 *
55 * Startup Code (reset vector)
56 *
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
59 * setup stack
60 * jump to second stage
61 *
62 *************************************************************************
63 */
64
Heiko Schocher296c3ee2010-09-17 13:10:49 +020065.globl _TEXT_BASE
wdenkb98ac282004-02-24 00:16:43 +000066_TEXT_BASE:
Wolfgang Denk0708bc62010-10-07 21:51:12 +020067 .word CONFIG_SYS_TEXT_BASE
wdenkb98ac282004-02-24 00:16:43 +000068
wdenkb98ac282004-02-24 00:16:43 +000069/*
wdenkc35ba4e2004-03-14 22:25:36 +000070 * These are defined in the board-specific linker script.
Albert Aribaud126897e2010-11-25 22:45:02 +010071 * Subtracting _start from them lets the linker put their
72 * relative position in the executable instead of leaving
73 * them null.
wdenkb98ac282004-02-24 00:16:43 +000074 */
Albert Aribaud126897e2010-11-25 22:45:02 +010075.globl _bss_start_ofs
76_bss_start_ofs:
77 .word __bss_start - _start
wdenkc35ba4e2004-03-14 22:25:36 +000078
Albert Aribaud126897e2010-11-25 22:45:02 +010079.globl _bss_end_ofs
80_bss_end_ofs:
Po-Yu Chuangcedbf4b2011-03-01 22:59:59 +000081 .word __bss_end__ - _start
wdenkb98ac282004-02-24 00:16:43 +000082
Po-Yu Chuang1864b002011-03-01 23:02:04 +000083.globl _end_ofs
84_end_ofs:
85 .word _end - _start
86
wdenkb98ac282004-02-24 00:16:43 +000087#ifdef CONFIG_USE_IRQ
88/* IRQ stack memory (calculated at run-time) */
89.globl IRQ_STACK_START
90IRQ_STACK_START:
91 .word 0x0badc0de
92
93/* IRQ stack memory (calculated at run-time) */
94.globl FIQ_STACK_START
95FIQ_STACK_START:
96 .word 0x0badc0de
97#endif
98
Heiko Schocher296c3ee2010-09-17 13:10:49 +020099/* IRQ stack memory (calculated at run-time) + 8 bytes */
100.globl IRQ_STACK_START_IN
101IRQ_STACK_START_IN:
102 .word 0x0badc0de
103
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200104/*
105 * the actual reset code
106 */
107
108reset:
109 /*
110 * set the cpu to SVC32 mode
111 */
112 mrs r0,cpsr
113 bic r0,r0,#0x1f
114 orr r0,r0,#0xd3
115 msr cpsr,r0
116
117 /*
118 * we do sys-critical inits only at reboot,
119 * not when booting from ram!
120 */
121#ifndef CONFIG_SKIP_LOWLEVEL_INIT
122 bl cpu_init_crit
123 /*
124 * before relocating, we have to setup RAM timing
125 * because memory timing is board-dependend, you will
126 * find a lowlevel_init.S in your board directory.
127 */
128 bl lowlevel_init
129#endif
130
131/* Set stackpointer in internal RAM to call board_init_f */
132call_board_init_f:
133 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
Heiko Schocher17f288a2010-11-12 07:53:55 +0100134 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200135 ldr r0,=0x00000000
136 bl board_init_f
137
138/*------------------------------------------------------------------------------*/
139
140/*
141 * void relocate_code (addr_sp, gd, addr_moni)
142 *
143 * This "function" does not return, instead it continues in RAM
144 * after relocating the monitor code.
145 *
146 */
147 .globl relocate_code
148relocate_code:
149 mov r4, r0 /* save addr_sp */
150 mov r5, r1 /* save addr of gd */
151 mov r6, r2 /* save addr of destination */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200152
153 /* Set up the stack */
154stack_setup:
155 mov sp, r4
156
157 adr r0, _start
Andreas Bießmann007b38f2010-12-01 00:58:34 +0100158 cmp r0, r6
Zhong Hongbo8c2ef802012-09-01 20:49:52 +0000159 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
Andreas Bießmann007b38f2010-12-01 00:58:34 +0100160 beq clear_bss /* skip relocation */
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100161 mov r1, r6 /* r1 <- scratch for copy_loop */
Albert Aribaud126897e2010-11-25 22:45:02 +0100162 ldr r3, _bss_start_ofs
163 add r2, r0, r3 /* r2 <- source end address */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200164
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200165copy_loop:
166 ldmia r0!, {r9-r10} /* copy from source address [r0] */
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100167 stmia r1!, {r9-r10} /* copy to target address [r1] */
Albert Aribaud0668d162010-10-05 16:06:39 +0200168 cmp r0, r2 /* until source end address [r2] */
169 blo copy_loop
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200170
Aneesh V552a3192011-07-13 05:11:07 +0000171#ifndef CONFIG_SPL_BUILD
Albert Aribaud126897e2010-11-25 22:45:02 +0100172 /*
173 * fix .rel.dyn relocations
174 */
175 ldr r0, _TEXT_BASE /* r0 <- Text base */
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100176 sub r9, r6, r0 /* r9 <- relocation offset */
Albert Aribaud126897e2010-11-25 22:45:02 +0100177 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
178 add r10, r10, r0 /* r10 <- sym table in FLASH */
179 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
180 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
181 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
182 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200183fixloop:
Albert Aribaud126897e2010-11-25 22:45:02 +0100184 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
185 add r0, r0, r9 /* r0 <- location to fix up in RAM */
186 ldr r1, [r2, #4]
Andreas Bießmann318cea12010-12-01 00:58:35 +0100187 and r7, r1, #0xff
188 cmp r7, #23 /* relative fixup? */
Albert Aribaud126897e2010-11-25 22:45:02 +0100189 beq fixrel
Andreas Bießmann318cea12010-12-01 00:58:35 +0100190 cmp r7, #2 /* absolute fixup? */
Albert Aribaud126897e2010-11-25 22:45:02 +0100191 beq fixabs
192 /* ignore unknown type of fixup */
193 b fixnext
194fixabs:
195 /* absolute fix: set location to (offset) symbol value */
196 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
197 add r1, r10, r1 /* r1 <- address of symbol in table */
198 ldr r1, [r1, #4] /* r1 <- symbol value */
Wolfgang Denk899cdd12010-12-09 11:26:24 +0100199 add r1, r1, r9 /* r1 <- relocated sym addr */
Albert Aribaud126897e2010-11-25 22:45:02 +0100200 b fixnext
201fixrel:
202 /* relative fix: increase location by offset */
203 ldr r1, [r0]
204 add r1, r1, r9
205fixnext:
206 str r1, [r0]
207 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200208 cmp r2, r3
Wolfgang Denk98dd07c2010-10-23 23:22:38 +0200209 blo fixloop
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200210#endif
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200211
212clear_bss:
Aneesh V552a3192011-07-13 05:11:07 +0000213#ifndef CONFIG_SPL_BUILD
Albert Aribaud126897e2010-11-25 22:45:02 +0100214 ldr r0, _bss_start_ofs
215 ldr r1, _bss_end_ofs
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100216 mov r4, r6 /* reloc addr */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200217 add r0, r0, r4
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200218 add r1, r1, r4
219 mov r2, #0x00000000 /* clear */
220
Zhong Hongbo1a324a52012-07-07 03:24:33 +0000221clbss_l:cmp r0, r1 /* clear loop... */
222 bhs clbss_e /* if reached end of bss, exit */
223 str r2, [r0]
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200224 add r0, r0, #4
Zhong Hongbo1a324a52012-07-07 03:24:33 +0000225 b clbss_l
226clbss_e:
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200227
228 bl coloured_LED_init
Jason Kridneraff0aa82011-09-04 14:40:16 -0400229 bl red_led_on
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200230#endif
231
232/*
233 * We are done. Do not return, instead branch to second part of board
234 * initialization, now running from RAM.
235 */
Albert Aribaud126897e2010-11-25 22:45:02 +0100236 ldr r0, _board_init_r_ofs
237 adr r1, _start
238 add lr, r0, r1
239 add lr, lr, r9
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200240 /* setup parameters for board_init_r */
241 mov r0, r5 /* gd_t */
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100242 mov r1, r6 /* dest_addr */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200243 /* jump to it ... */
Heiko Schocher296c3ee2010-09-17 13:10:49 +0200244 mov pc, lr
245
Albert Aribaud126897e2010-11-25 22:45:02 +0100246_board_init_r_ofs:
247 .word board_init_r - _start
248
249_rel_dyn_start_ofs:
250 .word __rel_dyn_start - _start
251_rel_dyn_end_ofs:
252 .word __rel_dyn_end - _start
253_dynsym_start_ofs:
254 .word __dynsym_start - _start
wdenkb98ac282004-02-24 00:16:43 +0000255
wdenkb98ac282004-02-24 00:16:43 +0000256/*
257 *************************************************************************
258 *
259 * CPU_init_critical registers
260 *
261 * setup important registers
262 * setup memory timing
263 *
264 *************************************************************************
265 */
266
267#define INTCON (0x01c00000+0x200000)
268#define INTMSK (0x01c00000+0x20000c)
269#define LOCKTIME (0x01c00000+0x18000c)
270#define PLLCON (0x01c00000+0x180000)
271#define CLKCON (0x01c00000+0x180004)
272#define WTCON (0x01c00000+0x130000)
273cpu_init_crit:
274 /* disable watch dog */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200275 ldr r0, =WTCON
wdenkb98ac282004-02-24 00:16:43 +0000276 ldr r1, =0x0
277 str r1, [r0]
278
279 /*
280 * mask all IRQs by clearing all bits in the INTMRs
281 */
282 ldr r1,=INTMSK
283 ldr r0, =0x03fffeff
284 str r0, [r1]
285
286 ldr r1, =INTCON
287 ldr r0, =0x05
288 str r0, [r1]
289
290 /* Set Clock Control Register */
291 ldr r1, =LOCKTIME
292 ldrb r0, =800
293 strb r0, [r1]
294
295 ldr r1, =PLLCON
296
297#if CONFIG_S3C44B0_CLOCK_SPEED==66
Wolfgang Denka1be4762008-05-20 16:00:29 +0200298 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
wdenkb98ac282004-02-24 00:16:43 +0000299#elif CONFIG_S3C44B0_CLOCK_SPEED==75
300 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
301#else
302# error CONFIG_S3C44B0_CLOCK_SPEED undefined
303#endif
304
305 str r0, [r1]
306
307 ldr r1,=CLKCON
308 ldr r0, =0x7ff8
309 str r0, [r1]
310
311 mov pc, lr
312
313
314/*************************************************/
315/* interrupt vectors */
316/*************************************************/
317real_vectors:
318 b reset
319 b undefined_instruction
320 b software_interrupt
321 b prefetch_abort
322 b data_abort
323 b not_used
324 b irq
325 b fiq
326
327/*************************************************/
328
329undefined_instruction:
330 mov r6, #3
331 b reset
332
333software_interrupt:
334 mov r6, #4
335 b reset
336
337prefetch_abort:
338 mov r6, #5
339 b reset
340
341data_abort:
342 mov r6, #6
343 b reset
344
345not_used:
346 /* we *should* never reach this */
347 mov r6, #7
348 b reset
349
350irq:
351 mov r6, #8
352 b reset
353
354fiq:
355 mov r6, #9
356 b reset