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git01.mediatek.com / filogic / uboot / 8ba732e6d8b3c2ff5271421d1ddd1025a73c4b38 / . / arch / arm / dts / imx7s-warp.dts
blob: db5ef67eb13005993c26fe05d6c1c2ec30358e3f [file] [log] [blame]
Bryan O'Donoghue5e23f992019-01-18 17:40:08 +0000[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 NXP Semiconductors.
4 * Author: Fabio Estevam <fabio.estevam@nxp.com>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/input/input.h>
10#include "imx7s.dtsi"
11
12/ {
13 model = "Warp i.MX7 Board";
14 compatible = "warp,imx7s-warp", "fsl,imx7s";
15
16 memory@80000000 {
17 reg = <0x80000000 0x20000000>;
18 };
19
Bryan O'Donoghue63b39bf2019-01-18 17:40:11 +0000[diff] [blame]20 aliases {
21 mmc0 = &usdhc3;
Pierre-Jean Texier8ba732e2019-04-19 20:34:12 +0200[diff] [blame^]22 usb0 = &usbotg1;
Bryan O'Donoghue63b39bf2019-01-18 17:40:11 +0000[diff] [blame]23 };
24
Pierre-Jean Texier297fc812019-04-19 20:34:11 +0200[diff] [blame]25 chosen {
26 stdout-path = &uart1;
27 };
28
Bryan O'Donoghue5e23f992019-01-18 17:40:08 +0000[diff] [blame]29 gpio-keys {
30 compatible = "gpio-keys";
31 pinctrl-0 = <&pinctrl_gpio>;
32 autorepeat;
33
34 back {
35 label = "Back";
36 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
37 linux,code = <KEY_BACK>;
38 wakeup-source;
39 };
40 };
41
42 reg_brcm: regulator-brcm {
43 compatible = "regulator-fixed";
44 enable-active-high;
45 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_brcm_reg>;
48 regulator-name = "brcm_reg";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 startup-delay-us = <200000>;
52 };
53
54 reg_bt: regulator-bt {
55 compatible = "regulator-fixed";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_bt_reg>;
58 enable-active-high;
59 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
60 regulator-name = "bt_reg";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 regulator-always-on;
64 };
65
66 sound {
67 compatible = "simple-audio-card";
68 simple-audio-card,name = "imx7-sgtl5000";
69 simple-audio-card,format = "i2s";
70 simple-audio-card,bitclock-master = <&dailink_master>;
71 simple-audio-card,frame-master = <&dailink_master>;
72 simple-audio-card,cpu {
73 sound-dai = <&sai1>;
74 };
75
76 dailink_master: simple-audio-card,codec {
77 sound-dai = <&codec>;
78 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
79 };
80 };
81};
82
83&clks {
84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
86};
87
88&i2c1 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_i2c1>;
91 status = "okay";
92
93 pmic: pfuze3000@8 {
94 compatible = "fsl,pfuze3000";
95 reg = <0x08>;
96
97 regulators {
98 sw1a_reg: sw1a {
99 regulator-min-microvolt = <700000>;
100 regulator-max-microvolt = <1475000>;
101 regulator-boot-on;
102 regulator-always-on;
103 regulator-ramp-delay = <6250>;
104 };
105
106 /* use sw1c_reg to align with pfuze100/pfuze200 */
107 sw1c_reg: sw1b {
108 regulator-min-microvolt = <700000>;
109 regulator-max-microvolt = <1475000>;
110 regulator-boot-on;
111 regulator-always-on;
112 regulator-ramp-delay = <6250>;
113 };
114
115 sw2_reg: sw2 {
116 regulator-min-microvolt = <1500000>;
117 regulator-max-microvolt = <1850000>;
118 regulator-boot-on;
119 regulator-always-on;
120 };
121
122 sw3a_reg: sw3 {
123 regulator-min-microvolt = <900000>;
124 regulator-max-microvolt = <1650000>;
125 regulator-boot-on;
126 regulator-always-on;
127 };
128
129 swbst_reg: swbst {
130 regulator-min-microvolt = <5000000>;
131 regulator-max-microvolt = <5150000>;
132 };
133
134 snvs_reg: vsnvs {
135 regulator-min-microvolt = <1000000>;
136 regulator-max-microvolt = <3000000>;
137 regulator-boot-on;
138 regulator-always-on;
139 };
140
141 vref_reg: vrefddr {
142 regulator-boot-on;
143 regulator-always-on;
144 };
145
146 vgen1_reg: vldo1 {
147 regulator-min-microvolt = <1800000>;
148 regulator-max-microvolt = <3300000>;
149 regulator-always-on;
150 };
151
152 vgen2_reg: vldo2 {
153 regulator-min-microvolt = <800000>;
154 regulator-max-microvolt = <1550000>;
155 };
156
157 vgen3_reg: vccsd {
158 regulator-min-microvolt = <2850000>;
159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
161 };
162
163 vgen4_reg: v33 {
164 regulator-min-microvolt = <2850000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
167 };
168
169 vgen5_reg: vldo3 {
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <3300000>;
172 regulator-always-on;
173 };
174
175 vgen6_reg: vldo4 {
176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <3300000>;
178 regulator-always-on;
179 };
180 };
181 };
182};
183
184&i2c2 {
185 clock-frequency = <100000>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_i2c2>;
188 status = "okay";
189};
190
191&i2c3 {
192 clock-frequency = <100000>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_i2c3>;
195 status = "okay";
196};
197
198&i2c4 {
199 clock-frequency = <100000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c4>;
202 status = "okay";
203
204 codec: sgtl5000@a {
205 #sound-dai-cells = <0>;
206 reg = <0x0a>;
207 compatible = "fsl,sgtl5000";
208 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_sai1_mclk>;
211 VDDA-supply = <&vgen4_reg>;
212 VDDIO-supply = <&vgen4_reg>;
213 VDDD-supply = <&vgen2_reg>;
214 };
215
216 mpl3115@60 {
217 compatible = "fsl,mpl3115";
218 reg = <0x60>;
219 };
220};
221
222&sai1 {
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_sai1>;
225 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
226 <&clks IMX7D_SAI1_ROOT_CLK>;
227 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
228 assigned-clock-rates = <0>, <36864000>;
229 status = "okay";
230};
231
232&uart1 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_uart1>;
235 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
236 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
237 status = "okay";
238};
239
240&uart3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart3>;
243 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
244 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
245 uart-has-rtscts;
246 status = "okay";
247};
248
249&uart6 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_uart6>;
252 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
253 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
254 fsl,dte-mode;
255 status = "okay";
256};
257
258&usbotg1 {
259 dr_mode = "peripheral";
260 status = "okay";
261};
262
263&usdhc1 {
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_usdhc1>;
266 bus-width = <4>;
267 keep-power-in-suspend;
268 no-1-8-v;
269 non-removable;
270 vmmc-supply = <&reg_brcm>;
271 status = "okay";
272};
273
274&usdhc3 {
275 pinctrl-names = "default", "state_100mhz", "state_200mhz";
276 pinctrl-0 = <&pinctrl_usdhc3>;
277 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
278 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
279 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
280 assigned-clock-rates = <400000000>;
281 bus-width = <8>;
282 no-1-8-v;
283 fsl,tuning-step = <2>;
284 non-removable;
285 status = "okay";
286};
287
288&wdog1 {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_wdog>;
291 fsl,ext-reset-output;
292 status = "okay";
293};
294
295&iomuxc {
296 pinctrl_brcm_reg: brcmreggrp {
297 fsl,pins = <
298 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
299 >;
300 };
301
302 pinctrl_bt_reg: btreggrp {
303 fsl,pins = <
304 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
305 >;
306 };
307
308 pinctrl_gpio: gpiogrp {
309 fsl,pins = <
310 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
311 >;
312 };
313
314 pinctrl_i2c1: i2c1grp {
315 fsl,pins = <
316 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
317 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
318 >;
319 };
320
321 pinctrl_i2c2: i2c2grp {
322 fsl,pins = <
323 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
324 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
325 >;
326 };
327
328 pinctrl_i2c3: i2c3grp {
329 fsl,pins = <
330 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
331 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
332 >;
333 };
334
335 pinctrl_i2c4: i2c4grp {
336 fsl,pins = <
337 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
338 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
339 >;
340 };
341
342 pinctrl_sai1: sai1grp {
343 fsl,pins = <
344 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
345 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
346 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
347 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
348 >;
349 };
350
351 pinctrl_sai1_mclk: sai1mclkgrp {
352 fsl,pins = <
353 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
354 >;
355 };
356
357 pinctrl_uart1: uart1grp {
358 fsl,pins = <
359 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
360 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
361 >;
362 };
363
364 pinctrl_uart3: uart3grp {
365 fsl,pins = <
366 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
367 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
368 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
369 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
370 >;
371 };
372
373 pinctrl_uart6: uart6grp {
374 fsl,pins = <
375 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
376 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
377 >;
378 };
379
380 pinctrl_usdhc1: usdhc1grp {
381 fsl,pins = <
382 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
383 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
384 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
385 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
386 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
387 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
388 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
389 >;
390 };
391
392 pinctrl_usdhc3: usdhc3grp {
393 fsl,pins = <
394 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
395 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
396 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
397 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
398 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
399 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
400 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
401 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
402 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
403 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
404 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
405 >;
406 };
407
408 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
409 fsl,pins = <
410 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
411 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
412 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
413 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
414 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
415 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
416 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
417 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
418 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
419 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
420 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
421 >;
422 };
423
424 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
425 fsl,pins = <
426 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
427 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
428 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
429 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
430 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
431 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
432 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
433 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
434 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
435 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
436 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
437 >;
438 };
439};
440
441&iomuxc_lpsr {
442 pinctrl_wdog: wdoggrp {
443 fsl,pins = <
444 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
445 >;
446 };
447};