Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 297fc81364b51832e6edd4e6c58c7b2b9e45a4f7 / . / arch / arm / dts / imx7s-warp.dts
blob: 4d87348f643ecbdd7ceabbb74b388fa91cc8fb73 [file] [log] [blame]
Bryan O'Donoghue5e23f992019-01-18 17:40:08 +0000[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 NXP Semiconductors.
4 * Author: Fabio Estevam <fabio.estevam@nxp.com>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/input/input.h>
10#include "imx7s.dtsi"
11
12/ {
13 model = "Warp i.MX7 Board";
14 compatible = "warp,imx7s-warp", "fsl,imx7s";
15
16 memory@80000000 {
17 reg = <0x80000000 0x20000000>;
18 };
19
Bryan O'Donoghue63b39bf2019-01-18 17:40:11 +0000[diff] [blame]20 aliases {
21 mmc0 = &usdhc3;
22 };
23
Pierre-Jean Texier297fc812019-04-19 20:34:11 +0200[diff] [blame^]24 chosen {
25 stdout-path = &uart1;
26 };
27
Bryan O'Donoghue5e23f992019-01-18 17:40:08 +0000[diff] [blame]28 gpio-keys {
29 compatible = "gpio-keys";
30 pinctrl-0 = <&pinctrl_gpio>;
31 autorepeat;
32
33 back {
34 label = "Back";
35 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
36 linux,code = <KEY_BACK>;
37 wakeup-source;
38 };
39 };
40
41 reg_brcm: regulator-brcm {
42 compatible = "regulator-fixed";
43 enable-active-high;
44 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_brcm_reg>;
47 regulator-name = "brcm_reg";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 startup-delay-us = <200000>;
51 };
52
53 reg_bt: regulator-bt {
54 compatible = "regulator-fixed";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_bt_reg>;
57 enable-active-high;
58 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
59 regulator-name = "bt_reg";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 regulator-always-on;
63 };
64
65 sound {
66 compatible = "simple-audio-card";
67 simple-audio-card,name = "imx7-sgtl5000";
68 simple-audio-card,format = "i2s";
69 simple-audio-card,bitclock-master = <&dailink_master>;
70 simple-audio-card,frame-master = <&dailink_master>;
71 simple-audio-card,cpu {
72 sound-dai = <&sai1>;
73 };
74
75 dailink_master: simple-audio-card,codec {
76 sound-dai = <&codec>;
77 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
78 };
79 };
80};
81
82&clks {
83 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
84 assigned-clock-rates = <884736000>;
85};
86
87&i2c1 {
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_i2c1>;
90 status = "okay";
91
92 pmic: pfuze3000@8 {
93 compatible = "fsl,pfuze3000";
94 reg = <0x08>;
95
96 regulators {
97 sw1a_reg: sw1a {
98 regulator-min-microvolt = <700000>;
99 regulator-max-microvolt = <1475000>;
100 regulator-boot-on;
101 regulator-always-on;
102 regulator-ramp-delay = <6250>;
103 };
104
105 /* use sw1c_reg to align with pfuze100/pfuze200 */
106 sw1c_reg: sw1b {
107 regulator-min-microvolt = <700000>;
108 regulator-max-microvolt = <1475000>;
109 regulator-boot-on;
110 regulator-always-on;
111 regulator-ramp-delay = <6250>;
112 };
113
114 sw2_reg: sw2 {
115 regulator-min-microvolt = <1500000>;
116 regulator-max-microvolt = <1850000>;
117 regulator-boot-on;
118 regulator-always-on;
119 };
120
121 sw3a_reg: sw3 {
122 regulator-min-microvolt = <900000>;
123 regulator-max-microvolt = <1650000>;
124 regulator-boot-on;
125 regulator-always-on;
126 };
127
128 swbst_reg: swbst {
129 regulator-min-microvolt = <5000000>;
130 regulator-max-microvolt = <5150000>;
131 };
132
133 snvs_reg: vsnvs {
134 regulator-min-microvolt = <1000000>;
135 regulator-max-microvolt = <3000000>;
136 regulator-boot-on;
137 regulator-always-on;
138 };
139
140 vref_reg: vrefddr {
141 regulator-boot-on;
142 regulator-always-on;
143 };
144
145 vgen1_reg: vldo1 {
146 regulator-min-microvolt = <1800000>;
147 regulator-max-microvolt = <3300000>;
148 regulator-always-on;
149 };
150
151 vgen2_reg: vldo2 {
152 regulator-min-microvolt = <800000>;
153 regulator-max-microvolt = <1550000>;
154 };
155
156 vgen3_reg: vccsd {
157 regulator-min-microvolt = <2850000>;
158 regulator-max-microvolt = <3300000>;
159 regulator-always-on;
160 };
161
162 vgen4_reg: v33 {
163 regulator-min-microvolt = <2850000>;
164 regulator-max-microvolt = <3300000>;
165 regulator-always-on;
166 };
167
168 vgen5_reg: vldo3 {
169 regulator-min-microvolt = <1800000>;
170 regulator-max-microvolt = <3300000>;
171 regulator-always-on;
172 };
173
174 vgen6_reg: vldo4 {
175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <3300000>;
177 regulator-always-on;
178 };
179 };
180 };
181};
182
183&i2c2 {
184 clock-frequency = <100000>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_i2c2>;
187 status = "okay";
188};
189
190&i2c3 {
191 clock-frequency = <100000>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c3>;
194 status = "okay";
195};
196
197&i2c4 {
198 clock-frequency = <100000>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_i2c4>;
201 status = "okay";
202
203 codec: sgtl5000@a {
204 #sound-dai-cells = <0>;
205 reg = <0x0a>;
206 compatible = "fsl,sgtl5000";
207 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_sai1_mclk>;
210 VDDA-supply = <&vgen4_reg>;
211 VDDIO-supply = <&vgen4_reg>;
212 VDDD-supply = <&vgen2_reg>;
213 };
214
215 mpl3115@60 {
216 compatible = "fsl,mpl3115";
217 reg = <0x60>;
218 };
219};
220
221&sai1 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_sai1>;
224 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
225 <&clks IMX7D_SAI1_ROOT_CLK>;
226 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
227 assigned-clock-rates = <0>, <36864000>;
228 status = "okay";
229};
230
231&uart1 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart1>;
234 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
235 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
236 status = "okay";
237};
238
239&uart3 {
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_uart3>;
242 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
243 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
244 uart-has-rtscts;
245 status = "okay";
246};
247
248&uart6 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_uart6>;
251 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
252 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
253 fsl,dte-mode;
254 status = "okay";
255};
256
257&usbotg1 {
258 dr_mode = "peripheral";
259 status = "okay";
260};
261
262&usdhc1 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_usdhc1>;
265 bus-width = <4>;
266 keep-power-in-suspend;
267 no-1-8-v;
268 non-removable;
269 vmmc-supply = <&reg_brcm>;
270 status = "okay";
271};
272
273&usdhc3 {
274 pinctrl-names = "default", "state_100mhz", "state_200mhz";
275 pinctrl-0 = <&pinctrl_usdhc3>;
276 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
277 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
278 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
279 assigned-clock-rates = <400000000>;
280 bus-width = <8>;
281 no-1-8-v;
282 fsl,tuning-step = <2>;
283 non-removable;
284 status = "okay";
285};
286
287&wdog1 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_wdog>;
290 fsl,ext-reset-output;
291 status = "okay";
292};
293
294&iomuxc {
295 pinctrl_brcm_reg: brcmreggrp {
296 fsl,pins = <
297 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
298 >;
299 };
300
301 pinctrl_bt_reg: btreggrp {
302 fsl,pins = <
303 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
304 >;
305 };
306
307 pinctrl_gpio: gpiogrp {
308 fsl,pins = <
309 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
310 >;
311 };
312
313 pinctrl_i2c1: i2c1grp {
314 fsl,pins = <
315 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
316 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
317 >;
318 };
319
320 pinctrl_i2c2: i2c2grp {
321 fsl,pins = <
322 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
323 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
324 >;
325 };
326
327 pinctrl_i2c3: i2c3grp {
328 fsl,pins = <
329 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
330 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
331 >;
332 };
333
334 pinctrl_i2c4: i2c4grp {
335 fsl,pins = <
336 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
337 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
338 >;
339 };
340
341 pinctrl_sai1: sai1grp {
342 fsl,pins = <
343 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
344 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
345 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
346 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
347 >;
348 };
349
350 pinctrl_sai1_mclk: sai1mclkgrp {
351 fsl,pins = <
352 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
353 >;
354 };
355
356 pinctrl_uart1: uart1grp {
357 fsl,pins = <
358 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
359 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
360 >;
361 };
362
363 pinctrl_uart3: uart3grp {
364 fsl,pins = <
365 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
366 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
367 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
368 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
369 >;
370 };
371
372 pinctrl_uart6: uart6grp {
373 fsl,pins = <
374 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
375 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
376 >;
377 };
378
379 pinctrl_usdhc1: usdhc1grp {
380 fsl,pins = <
381 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
382 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
383 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
384 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
385 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
386 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
387 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
388 >;
389 };
390
391 pinctrl_usdhc3: usdhc3grp {
392 fsl,pins = <
393 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
394 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
395 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
396 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
397 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
398 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
399 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
400 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
401 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
402 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
403 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
404 >;
405 };
406
407 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
408 fsl,pins = <
409 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
410 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
411 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
412 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
413 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
414 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
415 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
416 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
417 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
418 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
419 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
420 >;
421 };
422
423 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
424 fsl,pins = <
425 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
426 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
427 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
428 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
429 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
430 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
431 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
432 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
433 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
434 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
435 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
436 >;
437 };
438};
439
440&iomuxc_lpsr {
441 pinctrl_wdog: wdoggrp {
442 fsl,pins = <
443 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
444 >;
445 };
446};