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git01.mediatek.com / filogic / uboot / 8ba3d406324aae2d9a3a94febfcf7ff94fcd722b / . / arch / arm / dts / imx6qdl-gw560x.dtsi
blob: 1e95267c974ff3117836bc98f11b244cfc53b161 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1/*
2 * Copyright 2017 Gateworks Corporation
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include <dt-bindings/gpio/gpio.h>
49#include <dt-bindings/input/input.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51
52/ {
53 /* these are used by bootloader for disabling nodes */
54 aliases {
55 led0 = &led0;
56 led1 = &led1;
57 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame]58 mmc0 = &usdhc2;
59 mmc1 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]60 ssi0 = &ssi1;
Tim Harvey69a53212021-07-24 10:40:36 -0700[diff] [blame]61 usb0 = &usbotg;
62 usb1 = &usbh1;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]63 };
64
65 chosen {
66 stdout-path = &uart2;
67 };
68
69 backlight-display {
70 compatible = "pwm-backlight";
71 pwms = <&pwm4 0 5000000>;
72 brightness-levels = <
73 0 1 2 3 4 5 6 7 8 9
74 10 11 12 13 14 15 16 17 18 19
75 20 21 22 23 24 25 26 27 28 29
76 30 31 32 33 34 35 36 37 38 39
77 40 41 42 43 44 45 46 47 48 49
78 50 51 52 53 54 55 56 57 58 59
79 60 61 62 63 64 65 66 67 68 69
80 70 71 72 73 74 75 76 77 78 79
81 80 81 82 83 84 85 86 87 88 89
82 90 91 92 93 94 95 96 97 98 99
83 100
84 >;
85 default-brightness-level = <100>;
86 };
87
88 backlight-keypad {
89 compatible = "gpio-backlight";
90 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
91 default-on;
92 };
93
94 gpio-keys {
95 compatible = "gpio-keys";
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 user-pb {
100 label = "user_pb";
101 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
102 linux,code = <BTN_0>;
103 };
104
105 user-pb1x {
106 label = "user_pb1x";
107 linux,code = <BTN_1>;
108 interrupt-parent = <&gsc>;
109 interrupts = <0>;
110 };
111
112 key-erased {
113 label = "key-erased";
114 linux,code = <BTN_2>;
115 interrupt-parent = <&gsc>;
116 interrupts = <1>;
117 };
118
119 eeprom-wp {
120 label = "eeprom_wp";
121 linux,code = <BTN_3>;
122 interrupt-parent = <&gsc>;
123 interrupts = <2>;
124 };
125
126 tamper {
127 label = "tamper";
128 linux,code = <BTN_4>;
129 interrupt-parent = <&gsc>;
130 interrupts = <5>;
131 };
132
133 switch-hold {
134 label = "switch_hold";
135 linux,code = <BTN_5>;
136 interrupt-parent = <&gsc>;
137 interrupts = <7>;
138 };
139 };
140
141 leds {
142 compatible = "gpio-leds";
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_gpio_leds>;
145
146 led0: user1 {
147 label = "user1";
148 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
149 default-state = "on";
150 linux,default-trigger = "heartbeat";
151 };
152
153 led1: user2 {
154 label = "user2";
155 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
156 default-state = "off";
157 };
158
159 led2: user3 {
160 label = "user3";
161 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
162 default-state = "off";
163 };
164 };
165
166 memory@10000000 {
167 device_type = "memory";
168 reg = <0x10000000 0x40000000>;
169 };
170
171 pps {
172 compatible = "pps-gpio";
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_pps>;
175 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
176 };
177
178 reg_2p5v: regulator-2p5v {
179 compatible = "regulator-fixed";
180 regulator-name = "2P5V";
181 regulator-min-microvolt = <2500000>;
182 regulator-max-microvolt = <2500000>;
183 regulator-always-on;
184 };
185
186 reg_3p3v: regulator-3p3v {
187 compatible = "regulator-fixed";
188 regulator-name = "3P3V";
189 regulator-min-microvolt = <3300000>;
190 regulator-max-microvolt = <3300000>;
191 regulator-always-on;
192 };
193
194 reg_5p0v: regulator-5p0v {
195 compatible = "regulator-fixed";
196 regulator-name = "5P0V";
197 regulator-min-microvolt = <5000000>;
198 regulator-max-microvolt = <5000000>;
199 regulator-always-on;
200 };
201
202 reg_12p0v: regulator-12p0v {
203 compatible = "regulator-fixed";
204 regulator-name = "12P0V";
205 regulator-min-microvolt = <12000000>;
206 regulator-max-microvolt = <12000000>;
207 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
208 enable-active-high;
209 };
210
211 reg_1p4v: regulator-vddsoc {
212 compatible = "regulator-fixed";
213 regulator-name = "vdd_soc";
214 regulator-min-microvolt = <1400000>;
215 regulator-max-microvolt = <1400000>;
216 regulator-always-on;
217 };
218
219 reg_usb_h1_vbus: regulator-usb-h1-vbus {
220 compatible = "regulator-fixed";
221 regulator-name = "usb_h1_vbus";
222 regulator-min-microvolt = <5000000>;
223 regulator-max-microvolt = <5000000>;
Tim Harvey469611e2021-09-29 15:04:22 -0700[diff] [blame]224 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
225 enable-active-high;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]226 };
227
228 reg_usb_otg_vbus: regulator-usb-otg-vbus {
229 compatible = "regulator-fixed";
230 regulator-name = "usb_otg_vbus";
231 regulator-min-microvolt = <5000000>;
232 regulator-max-microvolt = <5000000>;
233 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
234 enable-active-high;
235 };
236
237 sound {
238 compatible = "fsl,imx6q-ventana-sgtl5000",
239 "fsl,imx-audio-sgtl5000";
240 model = "sgtl5000-audio";
241 ssi-controller = <&ssi1>;
242 audio-codec = <&sgtl5000>;
243 audio-routing =
244 "MIC_IN", "Mic Jack",
245 "Mic Jack", "Mic Bias",
246 "Headphone Jack", "HP_OUT";
247 mux-int-port = <1>;
248 mux-ext-port = <4>;
249 };
250};
251
252&audmux {
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_audmux>;
255 status = "okay";
256};
257
258&ecspi3 {
259 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_ecspi3>;
262 status = "okay";
263};
264
265&can1 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_flexcan>;
268 status = "okay";
269};
270
271&clks {
272 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
273 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
274 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
275 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
276};
277
278&fec {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_enet>;
281 phy-mode = "rgmii-id";
282 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harvey6ce10d52021-05-03 11:21:27 -0700[diff] [blame]283 phy-reset-duration = <10>;
284 phy-reset-post-delay = <100>;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]285 status = "okay";
286};
287
288&hdmi {
289 ddc-i2c-bus = <&i2c3>;
290 status = "okay";
291};
292
293&i2c1 {
294 clock-frequency = <100000>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_i2c1>;
297 status = "okay";
298
299 gsc: gsc@20 {
300 compatible = "gw,gsc";
301 reg = <0x20>;
302 interrupt-parent = <&gpio1>;
303 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
304 interrupt-controller;
305 #interrupt-cells = <1>;
306 #size-cells = <0>;
307
308 adc {
309 compatible = "gw,gsc-adc";
310 #address-cells = <1>;
311 #size-cells = <0>;
312
313 channel@0 {
314 gw,mode = <0>;
315 reg = <0x00>;
316 label = "temp";
317 };
318
319 channel@2 {
320 gw,mode = <1>;
321 reg = <0x02>;
322 label = "vdd_vin";
323 };
324
325 channel@5 {
326 gw,mode = <1>;
327 reg = <0x05>;
328 label = "vdd_3p3";
329 };
330
331 channel@8 {
332 gw,mode = <1>;
333 reg = <0x08>;
334 label = "vdd_bat";
335 };
336
337 channel@b {
338 gw,mode = <1>;
339 reg = <0x0b>;
340 label = "vdd_5p0";
341 };
342
343 channel@e {
344 gw,mode = <1>;
345 reg = <0xe>;
346 label = "vdd_arm";
347 };
348
349 channel@11 {
350 gw,mode = <1>;
351 reg = <0x11>;
352 label = "vdd_soc";
353 };
354
355 channel@14 {
356 gw,mode = <1>;
357 reg = <0x14>;
358 label = "vdd_3p0";
359 };
360
361 channel@17 {
362 gw,mode = <1>;
363 reg = <0x17>;
364 label = "vdd_1p5";
365 };
366
367 channel@1d {
368 gw,mode = <1>;
369 reg = <0x1d>;
370 label = "vdd_1p8";
371 };
372
373 channel@20 {
374 gw,mode = <1>;
375 reg = <0x20>;
376 label = "vdd_an1";
377 };
378
379 channel@23 {
380 gw,mode = <1>;
381 reg = <0x23>;
382 label = "vdd_2p5";
383 };
384
385 channel@26 {
386 gw,mode = <1>;
387 reg = <0x26>;
388 label = "vdd_gps";
389 };
390
391 channel@29 {
392 gw,mode = <1>;
393 reg = <0x29>;
394 label = "vdd_an2";
395 };
396 };
397 };
398
399 gsc_gpio: gpio@23 {
400 compatible = "nxp,pca9555";
401 reg = <0x23>;
402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-parent = <&gsc>;
405 interrupts = <4>;
406 };
407
408 eeprom1: eeprom@50 {
409 compatible = "atmel,24c02";
410 reg = <0x50>;
411 pagesize = <16>;
412 };
413
414 eeprom2: eeprom@51 {
415 compatible = "atmel,24c02";
416 reg = <0x51>;
417 pagesize = <16>;
418 };
419
420 eeprom3: eeprom@52 {
421 compatible = "atmel,24c02";
422 reg = <0x52>;
423 pagesize = <16>;
424 };
425
426 eeprom4: eeprom@53 {
427 compatible = "atmel,24c02";
428 reg = <0x53>;
429 pagesize = <16>;
430 };
431
432 ds1672: rtc@68 {
433 compatible = "dallas,ds1672";
434 reg = <0x68>;
435 };
436};
437
438&i2c2 {
439 clock-frequency = <100000>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_i2c2>;
442 status = "okay";
443
444 sgtl5000: codec@a {
445 compatible = "fsl,sgtl5000";
446 reg = <0x0a>;
447 #sound-dai-cells = <0>;
448 clocks = <&clks IMX6QDL_CLK_CKO>;
449 VDDA-supply = <&reg_1p8v>;
450 VDDIO-supply = <&reg_3p3v>;
451 };
452
453 magn@1c {
454 compatible = "st,lsm9ds1-magn";
455 reg = <0x1c>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&pinctrl_mag>;
458 interrupt-parent = <&gpio5>;
459 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
460 };
461
462 tca8418: keypad@34 {
463 compatible = "ti,tca8418";
464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_keypad>;
466 reg = <0x34>;
467 interrupt-parent = <&gpio5>;
468 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
469 linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
470 MATRIX_KEY(0x00, 0x00, BTN_1)
471 MATRIX_KEY(0x01, 0x01, BTN_2)
472 MATRIX_KEY(0x01, 0x00, BTN_3)
473 MATRIX_KEY(0x02, 0x00, BTN_4)
474 MATRIX_KEY(0x00, 0x03, BTN_5)
475 MATRIX_KEY(0x00, 0x02, BTN_6)
476 MATRIX_KEY(0x01, 0x03, BTN_7)
477 MATRIX_KEY(0x01, 0x02, BTN_8)
478 MATRIX_KEY(0x02, 0x02, BTN_9)
479 >;
480 keypad,num-rows = <4>;
481 keypad,num-columns = <4>;
482 };
483
484 ltc3676: pmic@3c {
485 compatible = "lltc,ltc3676";
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_pmic>;
488 reg = <0x3c>;
489 interrupt-parent = <&gpio1>;
490 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
491
492 regulators {
493 /* VDD_DDR (1+R1/R2 = 2.105) */
494 reg_vdd_ddr: sw2 {
495 regulator-name = "vddddr";
496 regulator-min-microvolt = <868310>;
497 regulator-max-microvolt = <1684000>;
498 lltc,fb-voltage-divider = <221000 200000>;
499 regulator-ramp-delay = <7000>;
500 regulator-boot-on;
501 regulator-always-on;
502 };
503
504 /* VDD_ARM (1+R1/R2 = 1.931) */
505 reg_vdd_arm: sw3 {
506 regulator-name = "vddarm";
507 regulator-min-microvolt = <796551>;
508 regulator-max-microvolt = <1544827>;
509 lltc,fb-voltage-divider = <243000 261000>;
510 regulator-ramp-delay = <7000>;
511 regulator-boot-on;
512 regulator-always-on;
513 linux,phandle = <&reg_vdd_arm>;
514 };
515
516 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
517 reg_1p8v: sw4 {
518 regulator-name = "vdd1p8";
519 regulator-min-microvolt = <1033310>;
520 regulator-max-microvolt = <2004000>;
521 lltc,fb-voltage-divider = <301000 200000>;
522 regulator-ramp-delay = <7000>;
523 regulator-boot-on;
524 regulator-always-on;
525 };
526
527 /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
528 reg_1p0v: ldo2 {
529 regulator-name = "vdd1p0";
530 regulator-min-microvolt = <950000>;
531 regulator-max-microvolt = <1050000>;
532 lltc,fb-voltage-divider = <78700 200000>;
533 regulator-boot-on;
534 regulator-always-on;
535 };
536
537 /* VDD_AUD_1P8: Audio codec */
538 reg_aud_1p8v: ldo3 {
539 regulator-name = "vdd1p8a";
540 regulator-min-microvolt = <1800000>;
541 regulator-max-microvolt = <1800000>;
542 regulator-boot-on;
543 };
544
545 /* VDD_HIGH (1+R1/R2 = 4.17) */
546 reg_3p0v: ldo4 {
547 regulator-name = "vdd3p0";
548 regulator-min-microvolt = <3023250>;
549 regulator-max-microvolt = <3023250>;
550 lltc,fb-voltage-divider = <634000 200000>;
551 regulator-boot-on;
552 regulator-always-on;
553 };
554 };
555 };
556
557 imu@6a {
558 compatible = "st,lsm9ds1-imu";
559 reg = <0x6a>;
560 st,drdy-int-pin = <1>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_imu>;
563 interrupt-parent = <&gpio5>;
564 interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
565 };
566};
567
568&i2c3 {
569 clock-frequency = <100000>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_i2c3>;
572 status = "okay";
573
574 egalax_ts: touchscreen@4 {
575 compatible = "eeti,egalax_ts";
576 reg = <0x04>;
577 interrupt-parent = <&gpio5>;
578 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
579 wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
580 };
581};
582
583&ldb {
584 fsl,dual-channel;
585 status = "okay";
586
587 lvds-channel@0 {
588 fsl,data-mapping = "spwg";
589 fsl,data-width = <18>;
590 status = "okay";
591
592 display-timings {
593 native-mode = <&timing0>;
594 timing0: hsd100pxn1 {
595 clock-frequency = <65000000>;
596 hactive = <1024>;
597 vactive = <768>;
598 hback-porch = <220>;
599 hfront-porch = <40>;
600 vback-porch = <21>;
601 vfront-porch = <7>;
602 hsync-len = <60>;
603 vsync-len = <10>;
604 };
605 };
606 };
607};
608
609&pcie {
610 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_pcie>;
612 reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
613 status = "okay";
614};
615
616&pwm2 {
617 pinctrl-names = "default";
618 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
619 status = "disabled";
620};
621
622&pwm3 {
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
625 status = "disabled";
626};
627
628&pwm4 {
629 #pwm-cells = <2>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_pwm4>;
632 status = "okay";
633};
634
635&ssi1 {
636 status = "okay";
637};
638
639&uart1 {
640 pinctrl-names = "default";
641 pinctrl-0 = <&pinctrl_uart1>;
642 uart-has-rtscts;
643 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
644 status = "okay";
645};
646
647&uart2 {
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_uart2>;
650 status = "okay";
651};
652
653&uart5 {
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_uart5>;
656 status = "okay";
657};
658
659&usbotg {
660 vbus-supply = <&reg_usb_otg_vbus>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_usbotg>;
663 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]664 dr_mode = "otg";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]665 status = "okay";
666};
667
668&usbh1 {
669 vbus-supply = <&reg_usb_h1_vbus>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_usbh1>;
672 status = "okay";
673};
674
675&usdhc2 {
676 pinctrl-names = "default";
677 pinctrl-0 = <&pinctrl_usdhc2>;
678 bus-width = <8>;
679 vmmc-supply = <&reg_3p3v>;
680 non-removable;
681 status = "okay";
682};
683
684&usdhc3 {
685 pinctrl-names = "default", "state_100mhz", "state_200mhz";
686 pinctrl-0 = <&pinctrl_usdhc3>;
687 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
688 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
689 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
690 vmmc-supply = <&reg_3p3v>;
691 status = "okay";
692};
693
694&wdog1 {
695 pinctrl-names = "default";
696 pinctrl-0 = <&pinctrl_wdog>;
697 fsl,ext-reset-output;
698};
699
700&iomuxc {
701 pinctrl_audmux: audmuxgrp {
702 fsl,pins = <
703 /* AUD4 */
704 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
705 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
706 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
707 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
708 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
709 /* AUD6 */
710 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
711 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
712 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
713 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
714 >;
715 };
716
717 pinctrl_ecspi3: escpi3grp {
718 fsl,pins = <
719 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
720 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
721 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
722 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
723 >;
724 };
725
726 pinctrl_enet: enetgrp {
727 fsl,pins = <
728 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
729 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
730 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
731 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
732 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
733 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
734 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
735 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
736 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
737 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
738 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
739 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
740 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
741 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
742 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
743 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
744 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
745 >;
746 };
747
748 pinctrl_flexcan: flexcangrp {
749 fsl,pins = <
750 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
751 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
752 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
753 >;
754 };
755
756 pinctrl_gpio_leds: gpioledsgrp {
757 fsl,pins = <
758 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
759 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
760 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
761 >;
762 };
763
764 pinctrl_i2c1: i2c1grp {
765 fsl,pins = <
766 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
767 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
768 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
769 >;
770 };
771
772 pinctrl_i2c2: i2c2grp {
773 fsl,pins = <
774 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
775 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
776 >;
777 };
778
779 pinctrl_i2c3: i2c3grp {
780 fsl,pins = <
781 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
782 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
783 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */
784 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */
785 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
786 >;
787 };
788
789 pinctrl_imu: imugrp {
790 fsl,pins = <
791 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
792 >;
793 };
794
795 pinctrl_keypad: keypadgrp {
796 fsl,pins = <
797 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
798 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
799 >;
800 };
801
802 pinctrl_mag: maggrp {
803 fsl,pins = <
804 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
805 >;
806 };
807
808 pinctrl_pcie: pciegrp {
809 fsl,pins = <
810 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
811 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
812 >;
813 };
814
815 pinctrl_pmic: pmicgrp {
816 fsl,pins = <
817 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
818 >;
819 };
820
821 pinctrl_pps: ppsgrp {
822 fsl,pins = <
823 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
824 >;
825 };
826
827 pinctrl_pwm2: pwm2grp {
828 fsl,pins = <
829 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
830 >;
831 };
832
833 pinctrl_pwm3: pwm3grp {
834 fsl,pins = <
835 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
836 >;
837 };
838
839 pinctrl_pwm4: pwm4grp {
840 fsl,pins = <
841 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
842 >;
843 };
844
845 pinctrl_uart1: uart1grp {
846 fsl,pins = <
847 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
848 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
849 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
850 >;
851 };
852
853 pinctrl_uart2: uart2grp {
854 fsl,pins = <
855 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
856 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
857 >;
858 };
859
860 pinctrl_uart5: uart5grp {
861 fsl,pins = <
862 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
863 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
864 >;
865 };
866
867 pinctrl_usbh1: usbh1grp {
868 fsl,pins = <
869 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */
870 >;
871 };
872
873 pinctrl_usbotg: usbotggrp {
874 fsl,pins = <
875 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
876 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
877 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
878 >;
879 };
880
881 pinctrl_usdhc2: usdhc2grp {
882 fsl,pins = <
883 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
884 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
885 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
886 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
887 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
888 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
889 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9
890 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9
891 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9
892 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9
893 >;
894 };
895
896 pinctrl_usdhc3: usdhc3grp {
897 fsl,pins = <
898 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
899 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
900 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
901 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
902 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
903 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
904 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
905 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
906 >;
907 };
908
909 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
910 fsl,pins = <
911 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
912 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
913 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
914 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
915 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
916 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
917 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
918 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
919 >;
920 };
921
922 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
923 fsl,pins = <
924 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
925 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
926 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
927 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
928 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
929 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
930 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
931 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
932 >;
933 };
934
935 pinctrl_wdog: wdoggrp {
936 fsl,pins = <
937 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
938 >;
939 };
940};