Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 1 | if ARCH_ROCKCHIP |
| 2 | |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 3 | config ROCKCHIP_RK3036 |
| 4 | bool "Support Rockchip RK3036" |
| 5 | select CPU_V7 |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 6 | select SUPPORT_SPL |
| 7 | select SPL |
Eddie Cai | a79b78f | 2018-01-17 09:51:41 +0800 | [diff] [blame] | 8 | imply USB_FUNCTION_ROCKUSB |
| 9 | imply CMD_ROCKUSB |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 10 | help |
| 11 | The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 |
| 12 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 13 | and video codec support. Peripherals include Gigabit Ethernet, |
| 14 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 15 | |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 16 | config ROCKCHIP_RK3128 |
| 17 | bool "Support Rockchip RK3128" |
| 18 | select CPU_V7 |
| 19 | help |
| 20 | The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 |
| 21 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 22 | and video codec support. Peripherals include Gigabit Ethernet, |
| 23 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 24 | |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 25 | config ROCKCHIP_RK3188 |
| 26 | bool "Support Rockchip RK3188" |
| 27 | select CPU_V7 |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 28 | select SPL_BOARD_INIT if SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 29 | select SUPPORT_SPL |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 30 | select SPL |
Philipp Tomsich | 5aa3f9d | 2017-10-10 16:21:17 +0200 | [diff] [blame] | 31 | select SPL_CLK |
| 32 | select SPL_PINCTRL |
| 33 | select SPL_REGMAP |
| 34 | select SPL_SYSCON |
| 35 | select SPL_RAM |
| 36 | select SPL_DRIVERS_MISC_SUPPORT |
Philipp Tomsich | 16c689c | 2017-10-10 16:21:15 +0200 | [diff] [blame] | 37 | select SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
Heiko Stübner | 015f69a | 2017-04-06 00:19:36 +0200 | [diff] [blame] | 38 | select BOARD_LATE_INIT |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 39 | select ROCKCHIP_BROM_HELPER |
| 40 | help |
| 41 | The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 |
| 42 | including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two |
| 43 | video interfaces, several memory options and video codec support. |
| 44 | Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, |
| 45 | UART, SPI, I2C and PWMs. |
| 46 | |
Kever Yang | 57d4dbf | 2017-06-23 17:17:52 +0800 | [diff] [blame] | 47 | config ROCKCHIP_RK322X |
| 48 | bool "Support Rockchip RK3228/RK3229" |
| 49 | select CPU_V7 |
| 50 | select SUPPORT_SPL |
| 51 | select SPL |
| 52 | select ROCKCHIP_BROM_HELPER |
| 53 | select DEBUG_UART_BOARD_INIT |
| 54 | help |
| 55 | The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 |
| 56 | including NEON and GPU, Mali-400 graphics, several DDR3 options |
| 57 | and video codec support. Peripherals include Gigabit Ethernet, |
| 58 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. |
| 59 | |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 60 | config ROCKCHIP_RK3288 |
| 61 | bool "Support Rockchip RK3288" |
Andreas Färber | 6c42703 | 2016-07-14 05:09:26 +0200 | [diff] [blame] | 62 | select CPU_V7 |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 63 | select SPL_BOARD_INIT if SPL |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 64 | select SUPPORT_SPL |
| 65 | select SPL |
Eddie Cai | b3501fe | 2017-12-15 08:17:13 +0800 | [diff] [blame] | 66 | imply USB_FUNCTION_ROCKUSB |
| 67 | imply CMD_ROCKUSB |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 68 | help |
| 69 | The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 |
| 70 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 71 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 72 | and video codec support. Peripherals include Gigabit Ethernet, |
Andreas Färber | 531e8e0 | 2016-11-02 18:03:01 +0100 | [diff] [blame] | 73 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 74 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 75 | config ROCKCHIP_RK3328 |
| 76 | bool "Support Rockchip RK3328" |
| 77 | select ARM64 |
| 78 | help |
| 79 | The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. |
| 80 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 81 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 82 | and video codec support. Peripherals include Gigabit Ethernet, |
| 83 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 84 | |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 85 | config ROCKCHIP_RK3368 |
| 86 | bool "Support Rockchip RK3368" |
| 87 | select ARM64 |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 88 | select SUPPORT_SPL |
| 89 | select SUPPORT_TPL |
Philipp Tomsich | 01b219e | 2017-07-28 20:03:07 +0200 | [diff] [blame] | 90 | select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL |
| 91 | select TPL_NEEDS_SEPARATE_STACK if TPL |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 92 | imply SPL_SEPARATE_BSS |
| 93 | imply SPL_SERIAL_SUPPORT |
| 94 | imply TPL_SERIAL_SUPPORT |
Philipp Tomsich | 84af43e | 2017-06-11 23:46:25 +0200 | [diff] [blame] | 95 | select DEBUG_UART_BOARD_INIT |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 96 | select SYS_NS16550 |
| 97 | help |
Philipp Tomsich | 9f3deaf | 2017-06-10 00:47:53 +0200 | [diff] [blame] | 98 | The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised |
| 99 | into a big and little cluster with 4 cores each) Cortex-A53 including |
| 100 | AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache |
| 101 | (for the little cluster), PowerVR G6110 based graphics, one video |
| 102 | output processor supporting LVDS/HDMI/eDP, several DDR3 options and |
| 103 | video codec support. |
| 104 | |
| 105 | On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, |
| 106 | I2S, UARTs, SPI, I2C and PWMs. |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 107 | |
Philipp Tomsich | cbacb40 | 2017-08-02 21:26:18 +0200 | [diff] [blame] | 108 | if ROCKCHIP_RK3368 |
| 109 | |
| 110 | config TPL_LDSCRIPT |
| 111 | default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" |
| 112 | |
Philipp Tomsich | 7d1319b | 2017-07-28 20:20:41 +0200 | [diff] [blame] | 113 | config TPL_TEXT_BASE |
| 114 | default 0xff8c1000 |
| 115 | |
| 116 | config TPL_MAX_SIZE |
| 117 | default 28672 |
| 118 | |
| 119 | config TPL_STACK |
| 120 | default 0xff8cffff |
| 121 | |
Philipp Tomsich | cbacb40 | 2017-08-02 21:26:18 +0200 | [diff] [blame] | 122 | endif |
| 123 | |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 124 | config ROCKCHIP_RK3399 |
| 125 | bool "Support Rockchip RK3399" |
| 126 | select ARM64 |
Kever Yang | 16efdfd | 2017-02-22 16:56:38 +0800 | [diff] [blame] | 127 | select SUPPORT_SPL |
| 128 | select SPL |
| 129 | select SPL_SEPARATE_BSS |
Philipp Tomsich | d17d8cf | 2017-07-26 12:29:01 +0200 | [diff] [blame] | 130 | select SPL_SERIAL_SUPPORT |
| 131 | select SPL_DRIVERS_MISC_SUPPORT |
Philipp Tomsich | 41029e6 | 2017-04-01 12:59:25 +0200 | [diff] [blame] | 132 | select DEBUG_UART_BOARD_INIT |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 133 | select BOARD_LATE_INIT |
Andy Yan | d2349d9 | 2017-10-11 15:00:49 +0800 | [diff] [blame] | 134 | select ROCKCHIP_BROM_HELPER |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 135 | help |
| 136 | The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 |
| 137 | and quad-core Cortex-A53. |
| 138 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two |
| 139 | video interfaces supporting HDMI and eDP, several DDR3 options |
| 140 | and video codec support. Peripherals include Gigabit Ethernet, |
| 141 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
| 142 | |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 143 | config ROCKCHIP_RV1108 |
| 144 | bool "Support Rockchip RV1108" |
| 145 | select CPU_V7 |
| 146 | help |
| 147 | The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 |
| 148 | and a DSP. |
| 149 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 150 | config SPL_ROCKCHIP_BACK_TO_BROM |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 151 | bool "SPL returns to bootrom" |
| 152 | default y if ROCKCHIP_RK3036 |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 153 | select ROCKCHIP_BROM_HELPER |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 154 | depends on SPL |
Xu Ziyuan | 5401eb8 | 2016-07-12 19:09:49 +0800 | [diff] [blame] | 155 | help |
| 156 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 157 | SPL will return to the boot rom, which will then load the U-Boot |
| 158 | binary to keep going on. |
| 159 | |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 160 | config TPL_ROCKCHIP_BACK_TO_BROM |
| 161 | bool "TPL returns to bootrom" |
| 162 | default y if ROCKCHIP_RK3368 |
| 163 | select ROCKCHIP_BROM_HELPER |
| 164 | depends on TPL |
| 165 | help |
| 166 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, |
| 167 | SPL will return to the boot rom, which will then load the U-Boot |
| 168 | binary to keep going on. |
| 169 | |
Andy Yan | 70378cb | 2017-10-11 15:00:16 +0800 | [diff] [blame] | 170 | config ROCKCHIP_BOOT_MODE_REG |
| 171 | hex "Rockchip boot mode flag register address" |
| 172 | default 0x200081c8 if ROCKCHIP_RK3036 |
| 173 | default 0x20004040 if ROCKCHIP_RK3188 |
| 174 | default 0x110005c8 if ROCKCHIP_RK322X |
| 175 | default 0xff730094 if ROCKCHIP_RK3288 |
| 176 | default 0xff738200 if ROCKCHIP_RK3368 |
| 177 | default 0xff320300 if ROCKCHIP_RK3399 |
| 178 | default 0x10300580 if ROCKCHIP_RV1108 |
| 179 | default 0 |
| 180 | help |
| 181 | The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) |
| 182 | according to the value from this register. |
| 183 | |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 184 | config ROCKCHIP_SPL_RESERVE_IRAM |
| 185 | hex "Size of IRAM reserved in SPL" |
Kever Yang | 60a5007 | 2017-12-18 15:13:19 +0800 | [diff] [blame] | 186 | default 0 |
Kever Yang | e484f77 | 2017-04-20 17:03:46 +0800 | [diff] [blame] | 187 | help |
| 188 | SPL may need reserve memory for firmware loaded by SPL, whose load |
| 189 | address is in IRAM and may overlay with SPL text area if not |
| 190 | reserved. |
| 191 | |
Heiko Stübner | 355a880 | 2017-02-18 19:46:25 +0100 | [diff] [blame] | 192 | config ROCKCHIP_BROM_HELPER |
| 193 | bool |
| 194 | |
Philipp Tomsich | 9f1a447 | 2017-10-10 16:21:10 +0200 | [diff] [blame] | 195 | config SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 196 | bool "SPL requires early-return (for RK3188-style BROM) to BROM" |
| 197 | depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 198 | help |
| 199 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 200 | first stage in segments and enter multiple times. E.g. on |
| 201 | the RK3188, the first 1KB of the first stage are loaded |
| 202 | first and entered; after returning to the BROM, the |
| 203 | remainder of the first stage is loaded, but the BROM |
| 204 | re-enters at the same address/to the same code as previously. |
| 205 | |
| 206 | This enables support code in the BOOT0 hook for the SPL stage |
| 207 | to allow multiple entries. |
| 208 | |
| 209 | config TPL_ROCKCHIP_EARLYRETURN_TO_BROM |
| 210 | bool "TPL requires early-return (for RK3188-style BROM) to BROM" |
| 211 | depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK |
| 212 | help |
| 213 | Some Rockchip BROM variants (e.g. on the RK3188) load the |
| 214 | first stage in segments and enter multiple times. E.g. on |
| 215 | the RK3188, the first 1KB of the first stage are loaded |
| 216 | first and entered; after returning to the BROM, the |
| 217 | remainder of the first stage is loaded, but the BROM |
| 218 | re-enters at the same address/to the same code as previously. |
| 219 | |
| 220 | This enables support code in the BOOT0 hook for the TPL stage |
| 221 | to allow multiple entries. |
| 222 | |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 223 | config SPL_MMC_SUPPORT |
Philipp Tomsich | 798370f | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 224 | default y if !SPL_ROCKCHIP_BACK_TO_BROM |
Sandy Patterson | d70f0f3 | 2016-08-29 07:31:16 -0400 | [diff] [blame] | 225 | |
huang lin | 1115b64 | 2015-11-17 14:20:27 +0800 | [diff] [blame] | 226 | source "arch/arm/mach-rockchip/rk3036/Kconfig" |
Kever Yang | aa82775 | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 227 | source "arch/arm/mach-rockchip/rk3128/Kconfig" |
Heiko Stübner | ef6db5e | 2017-02-18 19:46:36 +0100 | [diff] [blame] | 228 | source "arch/arm/mach-rockchip/rk3188/Kconfig" |
Kever Yang | a4f460d | 2017-06-23 17:17:54 +0800 | [diff] [blame] | 229 | source "arch/arm/mach-rockchip/rk322x/Kconfig" |
Heiko Stübner | 5c91e2b | 2016-07-16 00:17:15 +0200 | [diff] [blame] | 230 | source "arch/arm/mach-rockchip/rk3288/Kconfig" |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 231 | source "arch/arm/mach-rockchip/rk3328/Kconfig" |
Andreas Färber | 9e3ad68 | 2017-05-15 17:51:18 +0800 | [diff] [blame] | 232 | source "arch/arm/mach-rockchip/rk3368/Kconfig" |
Kever Yang | 0d3d783 | 2016-07-19 21:16:59 +0800 | [diff] [blame] | 233 | source "arch/arm/mach-rockchip/rk3399/Kconfig" |
Andy Yan | 2d982da | 2017-06-01 18:00:55 +0800 | [diff] [blame] | 234 | source "arch/arm/mach-rockchip/rv1108/Kconfig" |
Simon Glass | 2cffe66 | 2015-08-30 16:55:38 -0600 | [diff] [blame] | 235 | endif |