Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 2 | /* |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 3 | * Common configuration settings for IGEP technology based boards |
| 4 | * |
| 5 | * (C) Copyright 2012 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 6 | * ISEE 2007 SL, <www.iseebcn.com> |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 7 | */ |
| 8 | |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 9 | #ifndef __IGEP00X0_H |
| 10 | #define __IGEP00X0_H |
| 11 | |
Enric Balletbò i Serra | ed11648 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 12 | #define CONFIG_NR_DRAM_BANKS 2 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 13 | |
Enric Balletbò i Serra | ed11648 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 14 | #include <configs/ti_omap3_common.h> |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 15 | |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 16 | /* |
| 17 | * We are only ever GP parts and will utilize all of the "downloaded image" |
| 18 | * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). |
| 19 | */ |
Enric Balletbo i Serra | 8aa10d4 | 2016-05-03 08:59:24 +0200 | [diff] [blame] | 20 | #undef CONFIG_SPL_TEXT_BASE |
Enric Balletbo i Serra | 8aa10d4 | 2016-05-03 08:59:24 +0200 | [diff] [blame] | 21 | #define CONFIG_SPL_TEXT_BASE 0x40200000 |
| 22 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 23 | #define CONFIG_MISC_INIT_R |
| 24 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 25 | #define CONFIG_REVISION_TAG 1 |
| 26 | |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 27 | /* GPIO banks */ |
| 28 | #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */ |
| 29 | #define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */ |
| 30 | |
| 31 | /* TPS65950 */ |
| 32 | #define PBIASLITEVMODE1 (1 << 8) |
| 33 | |
| 34 | /* LED */ |
| 35 | #define IGEP0020_GPIO_LED 27 |
| 36 | #define IGEP0030_GPIO_LED 16 |
| 37 | |
| 38 | /* Board and revision detection GPIOs */ |
| 39 | #define IGEP0030_USB_TRANSCEIVER_RESET 54 |
| 40 | #define GPIO_IGEP00X0_BOARD_DETECTION 28 |
| 41 | #define GPIO_IGEP00X0_REVISION_DETECTION 129 |
Javier Martinez Canillas | d549ace | 2012-12-27 03:36:01 +0000 | [diff] [blame] | 42 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 43 | /* USB device configuration */ |
| 44 | #define CONFIG_USB_DEVICE 1 |
| 45 | #define CONFIG_USB_TTY 1 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 46 | |
| 47 | /* Change these to suit your needs */ |
| 48 | #define CONFIG_USBD_VENDORID 0x0451 |
| 49 | #define CONFIG_USBD_PRODUCTID 0x5678 |
| 50 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" |
| 51 | #define CONFIG_USBD_PRODUCT_NAME "IGEP" |
| 52 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 53 | #ifndef CONFIG_SPL_BUILD |
| 54 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 55 | /* Environment */ |
| 56 | #define ENV_DEVICE_SETTINGS \ |
| 57 | "stdin=serial\0" \ |
| 58 | "stdout=serial\0" \ |
| 59 | "stderr=serial\0" |
| 60 | |
| 61 | #define MEM_LAYOUT_SETTINGS \ |
| 62 | DEFAULT_LINUX_BOOT_ENV \ |
| 63 | "scriptaddr=0x87E00000\0" \ |
| 64 | "pxefile_addr_r=0x87F00000\0" |
| 65 | |
| 66 | #define BOOT_TARGET_DEVICES(func) \ |
| 67 | func(MMC, mmc, 0) |
| 68 | |
| 69 | #include <config_distro_bootcmd.h> |
| 70 | |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 71 | #define ENV_FINDFDT \ |
| 72 | "findfdt="\ |
| 73 | "if test ${board_name} = igep0020; then " \ |
| 74 | "if test ${board_rev} = F; then " \ |
| 75 | "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ |
| 76 | "else " \ |
| 77 | "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ |
| 78 | "if test ${board_name} = igep0030; then " \ |
| 79 | "if test ${board_rev} = G; then " \ |
| 80 | "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ |
| 81 | "else " \ |
| 82 | "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ |
| 83 | "if test ${fdtfile} = ''; then " \ |
| 84 | "echo WARNING: Could not determine device tree to use; fi; \0" |
| 85 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 86 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 87 | ENV_FINDFDT \ |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 88 | ENV_DEVICE_SETTINGS \ |
| 89 | MEM_LAYOUT_SETTINGS \ |
| 90 | BOOTENV |
Enric Balletbo i Serra | 4adf801 | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 91 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 92 | #endif |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 93 | |
Ladislav Michl | c44e29f | 2016-07-12 20:28:33 +0200 | [diff] [blame] | 94 | #define CONFIG_SYS_MTDPARTS_RUNTIME |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 95 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 96 | /* OneNAND config */ |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 97 | #define CONFIG_USE_ONENAND_BOARD_INIT |
| 98 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
| 99 | #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 100 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 101 | /* NAND config */ |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 102 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 103 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 104 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
| 105 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 106 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 107 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS |
| 108 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ |
| 109 | 10, 11, 12, 13, 14, 15, 16, 17, \ |
| 110 | 18, 19, 20, 21, 22, 23, 24, 25, \ |
| 111 | 26, 27, 28, 29, 30, 31, 32, 33, \ |
| 112 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
| 113 | 42, 43, 44, 45, 46, 47, 48, 49, \ |
| 114 | 50, 51, 52, 53, 54, 55, 56, 57, } |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 115 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_NAND_ECCBYTES 14 |
| 117 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 118 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 119 | /* UBI configuration */ |
| 120 | #define CONFIG_SPL_UBI 1 |
| 121 | #define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 |
| 122 | #define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) |
| 123 | #define CONFIG_SPL_UBI_MAX_PEBS 4096 |
| 124 | #define CONFIG_SPL_UBI_VOL_IDS 8 |
| 125 | #define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0 |
| 126 | #define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3 |
| 127 | #define CONFIG_SPL_UBI_LOAD_ARGS_ID 4 |
| 128 | #define CONFIG_SPL_UBI_PEB_OFFSET 4 |
| 129 | #define CONFIG_SPL_UBI_VID_OFFSET 512 |
| 130 | #define CONFIG_SPL_UBI_LEB_START 2048 |
| 131 | #define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 |
| 132 | |
| 133 | /* environment organization */ |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 134 | #define CONFIG_ENV_UBI_PART "UBI" |
| 135 | #define CONFIG_ENV_UBI_VOLUME "config" |
| 136 | #define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 137 | #define CONFIG_ENV_SIZE (32*1024) |
| 138 | |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 139 | #endif /* __IGEP00X0_H */ |