blob: 4ad4ee69c7c7fd83e59c3ca70469664003a42378 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard73ef2f02017-12-12 09:49:44 +01002/*
3 * Copyright (C) STMicroelectronics SA 2017
Patrice Chotard5d9950d2020-12-02 18:47:30 +01004 * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotard73ef2f02017-12-12 09:49:44 +01005 */
6
7#include <common.h>
8#include <dm.h>
Simon Glassed38aef2020-05-10 11:40:03 -06009#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Patrice Chotard73ef2f02017-12-12 09:49:44 +010012
13#include <asm/io.h>
14#include <asm/arch/stm32.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18int dram_init(void)
19{
20 int rv;
21 struct udevice *dev;
22
23 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
24 if (rv) {
25 debug("DRAM init failed: %d\n", rv);
26 return rv;
27 }
28
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053029 if (fdtdec_setup_mem_size_base() != 0)
Patrice Chotard73ef2f02017-12-12 09:49:44 +010030 rv = -EINVAL;
31
32 return rv;
33}
34
35int dram_init_banksize(void)
36{
37 fdtdec_setup_memory_banksize();
38
39 return 0;
40}
41
42u32 get_board_rev(void)
43{
44 return 0;
45}
46
47int board_early_init_f(void)
48{
49 return 0;
50}
51
52int board_init(void)
53{
Patrice Chotarda66c1b42018-08-03 11:46:11 +020054 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
Patrice Chotard73ef2f02017-12-12 09:49:44 +010055
56 return 0;
57}
58
59#ifdef CONFIG_MISC_INIT_R
60int misc_init_r(void)
61{
62 char serialno[25];
63 u32 u_id_low, u_id_mid, u_id_high;
64
65 if (!env_get("serial#")) {
66 u_id_low = readl(&STM32_U_ID->u_id_low);
67 u_id_mid = readl(&STM32_U_ID->u_id_mid);
68 u_id_high = readl(&STM32_U_ID->u_id_high);
69 sprintf(serialno, "%08x%08x%08x",
70 u_id_high, u_id_mid, u_id_low);
71 env_set("serial#", serialno);
72 }
73
74 return 0;
75}
76#endif