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git01.mediatek.com / filogic / uboot / 8a03b0dbd77a9cdaddc8e478495842aa939981bc / . / arch / arm / mach-uniphier / arm32 / debug_ll.S
blob: 3fed7985fcd63410e76b58d2162cdaf8b1c3909f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]2/*
3 * On-chip UART initializaion for low-level debugging
4 *
5 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]6 */
7
8#include <linux/serial_reg.h>
9#include <linux/linkage.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +0900[diff] [blame]10
Masahiro Yamada3119eb42016-02-26 18:59:44 +0900[diff] [blame]11#include "../bcu/bcu-regs.h"
12#include "../sc-regs.h"
13#include "../sg-regs.h"
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]14
15#if !defined(CONFIG_DEBUG_SEMIHOSTING)
16#include CONFIG_DEBUG_LL_INCLUDE
17#endif
18
Masahiro Yamada0ae28652019-06-29 02:38:01 +0900[diff] [blame]19#define SG_REVISION_TYPE_SHIFT 16
20#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]21#define BAUDRATE 115200
22#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
23
Masahiro Yamada3cac7f72019-06-29 02:38:06 +0900[diff] [blame]24.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]25 ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
Masahiro Yamada3cac7f72019-06-29 02:38:06 +0900[diff] [blame]26 ldr \rd, [\ra]
27 and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
28 orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
29 str \rd, [\ra]
30.endm
31
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]32ENTRY(debug_ll_init)
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]33 ldr r0, =(SG_BASE + SG_REVISION)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]34 ldr r1, [r0]
35 and r1, r1, #SG_REVISION_TYPE_MASK
36 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
37
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]38#if defined(CONFIG_ARCH_UNIPHIER_LD4)
39#define UNIPHIER_LD4_UART_CLK 36864000
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]40 cmp r1, #0x26
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]41 bne ld4_end
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]42
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]43 ldr r0, =(SG_BASE + SG_IECTRL)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]44 ldr r1, [r0]
45 orr r1, r1, #1
46 str r1, [r0]
47
48 sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
49
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]50 ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]51
52 b init_uart
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]53ld4_end:
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]54#endif
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]55#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
56#define UNIPHIER_PRO4_UART_CLK 73728000
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]57 cmp r1, #0x28
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]58 bne pro4_end
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]59
60 sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
61
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]62 ldr r0, =(SG_BASE + SG_LOADPINCTRL)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]63 mov r1, #1
64 str r1, [r0]
65
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]66 ldr r0, =(SC_BASE + SC_CLKCTRL)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]67 ldr r1, [r0]
68 orr r1, r1, #SC_CLKCTRL_CEN_PERI
69 str r1, [r0]
70
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]71 ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]72
73 b init_uart
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]74pro4_end:
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]75#endif
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]76#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
77#define UNIPHIER_SLD8_UART_CLK 80000000
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]78 cmp r1, #0x29
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]79 bne sld8_end
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]80
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]81 ldr r0, =(SG_BASE + SG_IECTRL)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]82 ldr r1, [r0]
83 orr r1, r1, #1
84 str r1, [r0]
85
86 sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
87
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]88 ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]89
90 b init_uart
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]91sld8_end:
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]92#endif
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]93#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
94#define UNIPHIER_PRO5_UART_CLK 73728000
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]95 cmp r1, #0x2A
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]96 bne pro5_end
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]97
98 sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
99 sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
100 sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
101 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
102
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]103 ldr r0, =(SG_BASE + SG_LOADPINCTRL)
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]104 mov r1, #1
105 str r1, [r0]
106
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]107 ldr r0, =(SC_BASE + SC_CLKCTRL)
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]108 ldr r1, [r0]
109 orr r1, r1, #SC_CLKCTRL_CEN_PERI
110 str r1, [r0]
111
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]112 ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]113
114 b init_uart
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]115pro5_end:
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]116#endif
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]117#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
118#define UNIPHIER_PXS2_UART_CLK 88900000
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]119 cmp r1, #0x2E
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]120 bne pxs2_end
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]121
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]122 ldr r0, =(SG_BASE + SG_IECTRL)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]123 ldr r1, [r0]
124 orr r1, r1, #1
125 str r1, [r0]
126
127 sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
128 sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
129 sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
130 sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
131
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]132 ldr r0, =(SC_BASE + SC_CLKCTRL)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]133 ldr r1, [r0]
134 orr r1, r1, #SC_CLKCTRL_CEN_PERI
135 str r1, [r0]
136
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]137 ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]138
139 b init_uart
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]140pxs2_end:
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]141#endif
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]142#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
143#define UNIPHIER_LD6B_UART_CLK 88900000
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]144 cmp r1, #0x2F
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]145 bne ld6b_end
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]146
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]147 ldr r0, =(SG_BASE + SG_IECTRL)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]148 ldr r1, [r0]
149 orr r1, r1, #1
150 str r1, [r0]
151
152 sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
153 sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
154 sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
155
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]156 ldr r0, =(SC_BASE + SC_CLKCTRL)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]157 ldr r1, [r0]
158 orr r1, r1, #SC_CLKCTRL_CEN_PERI
159 str r1, [r0]
160
Masahiro Yamada53c59ae2016-03-18 16:41:43 +0900[diff] [blame]161 ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]162
163 b init_uart
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]164ld6b_end:
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]165#endif
Masahiro Yamadaa8ea60d2016-03-07 20:29:41 +0900[diff] [blame]166 mov pc, lr
Masahiro Yamadac7432492015-09-22 00:27:37 +0900[diff] [blame]167
168init_uart:
169 addruart r0, r1, r2
170 mov r1, #UART_LCR_WLEN8 << 8
171 str r1, [r0, #0x10]
172 str r3, [r0, #0x24]
173
174 mov pc, lr
175ENDPROC(debug_ll_init)