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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stelian Popd1aea1c2008-01-30 21:15:54 +00002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Popd1aea1c2008-01-30 21:15:54 +00005 * Lead Tech Design <www.leadtechdesign.com>
Stelian Popd1aea1c2008-01-30 21:15:54 +00006 */
7
8#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glassa9dc0682019-12-28 10:44:59 -070010#include <time.h>
Reinhard Meyerb06208c2010-11-07 13:26:14 +010011#include <asm/io.h>
Stelian Popd1aea1c2008-01-30 21:15:54 +000012#include <asm/arch/hardware.h>
Stelian Popd4bfbc52008-03-26 20:52:32 +010013#include <asm/arch/at91_pit.h>
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020014#include <asm/arch/clk.h>
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020015#include <div64.h>
Stelian Popd1aea1c2008-01-30 21:15:54 +000016
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020017#if !defined(CONFIG_AT91FAMILY)
18# error You need to define CONFIG_AT91FAMILY in your board config!
19#endif
20
21DECLARE_GLOBAL_DATA_PTR;
22
Stelian Popd1aea1c2008-01-30 21:15:54 +000023/*
Stelian Popeea44aa2008-03-26 20:52:28 +010024 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
Stelian Popd1aea1c2008-01-30 21:15:54 +000025 * setting the 20 bit counter period to its maximum (0xfffff).
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020026 * (See the relevant data sheets to understand that this really works)
27 *
28 * We do also mimic the typical powerpc way of incrementing
29 * two 32 bit registers called tbl and tbu.
30 *
31 * Those registers increment at 1/16 the main clock rate.
Stelian Popd1aea1c2008-01-30 21:15:54 +000032 */
Stelian Popd1aea1c2008-01-30 21:15:54 +000033
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020034#define TIMER_LOAD_VAL 0xfffff
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020035
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020036/*
37 * Use the PITC in full 32 bit incrementing mode
38 */
Stelian Pop6bf2de22008-03-26 21:52:27 +010039int timer_init(void)
Stelian Popd1aea1c2008-01-30 21:15:54 +000040{
Reinhard Meyere260d0b2010-11-03 15:39:55 +010041 at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020042
Wenyou Yang57b7f292016-02-03 10:16:49 +080043 at91_periph_clk_enable(ATMEL_ID_SYS);
Stelian Popd1aea1c2008-01-30 21:15:54 +000044
45 /* Enable PITC */
Jens Scharsiga4db1ca2010-02-03 22:46:58 +010046 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
Stelian Popd1aea1c2008-01-30 21:15:54 +000047
Simon Glass6ed6e032012-12-13 20:48:32 +000048 gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
Jean-Christophe PLAGNIOL-VILLARD1d4a3792009-04-16 21:30:48 +020049
Stelian Popd1aea1c2008-01-30 21:15:54 +000050 return 0;
51}
52
53/*
Reinhard Meyer0a1790a2010-10-05 16:54:35 +020054 * Return the number of timer ticks per second.
Stelian Popd1aea1c2008-01-30 21:15:54 +000055 */
56ulong get_tbclk(void)
57{
Simon Glass6ed6e032012-12-13 20:48:32 +000058 return gd->arch.timer_rate_hz;
Stelian Popd1aea1c2008-01-30 21:15:54 +000059}