blob: b25f759c79d4c40bc53f0e6d7cc76761d7e6f277 [file] [log] [blame]
Simon Glass5f8865f2015-03-02 12:40:54 -07001/dts-v1/;
2
3/include/ "skeleton.dtsi"
4/include/ "serial.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -07005/include/ "reset.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +08006/include/ "rtc.dtsi"
Simon Glass5f8865f2015-03-02 12:40:54 -07007
Bin Meng8967f632021-07-28 12:00:23 +08008#include "tsc_timer.dtsi"
Simon Glassbee77f62020-11-05 06:32:17 -07009#include "smbios.dtsi"
10
Simon Glass5f8865f2015-03-02 12:40:54 -070011/ {
12 model = "Google Panther";
13 compatible = "google,panther", "intel,haswell";
14
15 aliases {
Bin Meng4f8d4e92016-01-27 00:56:34 -080016 spi0 = &spi;
Simon Glass5f8865f2015-03-02 12:40:54 -070017 };
18
19 config {
20 silent-console = <0>;
21 no-keyboard;
22 };
23
Simon Glass5f8865f2015-03-02 12:40:54 -070024 chosen {
25 stdout-path = "/serial";
26 };
27
Simon Glassa1a969e2015-08-27 19:54:48 -060028 pci {
29 compatible = "pci-x86";
30 #address-cells = <3>;
31 #size-cells = <2>;
32 u-boot,dm-pre-reloc;
33 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
34 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
35 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
Simon Glass32761632016-01-18 20:19:21 -070036
37 pch@1f,0 {
38 reg = <0x0000f800 0 0 0 0>;
39 compatible = "intel,pch9";
Bin Meng6e916cc2016-02-01 01:40:47 -080040 #address-cells = <1>;
41 #size-cells = <1>;
Simon Glassa1a969e2015-08-27 19:54:48 -060042
Bin Meng4f8d4e92016-01-27 00:56:34 -080043 spi: spi {
Simon Glass32761632016-01-18 20:19:21 -070044 #address-cells = <1>;
45 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -080046 compatible = "intel,ich9-spi";
Simon Glass32761632016-01-18 20:19:21 -070047 spi-flash@0 {
48 #size-cells = <1>;
49 #address-cells = <1>;
50 reg = <0>;
Bin Mengac54e252021-07-29 20:18:23 +080051 m25p,fast-read;
Simon Glass32761632016-01-18 20:19:21 -070052 compatible = "winbond,w25q64",
Neil Armstrongf6625b42019-02-10 10:16:21 +000053 "jedec,spi-nor";
Simon Glass32761632016-01-18 20:19:21 -070054 memory-map = <0xff800000 0x00800000>;
55 rw-mrc-cache {
56 label = "rw-mrc-cache";
57 reg = <0x003e0000 0x00010000>;
58 };
59 };
Simon Glass5f8865f2015-03-02 12:40:54 -070060 };
Bin Meng6e916cc2016-02-01 01:40:47 -080061
62 gpioa {
63 compatible = "intel,ich6-gpio";
64 u-boot,dm-pre-reloc;
65 reg = <0 0x10>;
66 bank-name = "A";
67 };
68
69 gpiob {
70 compatible = "intel,ich6-gpio";
71 u-boot,dm-pre-reloc;
72 reg = <0x30 0x10>;
73 bank-name = "B";
74 };
75
76 gpioc {
77 compatible = "intel,ich6-gpio";
78 u-boot,dm-pre-reloc;
79 reg = <0x40 0x10>;
80 bank-name = "C";
81 };
Simon Glass5f8865f2015-03-02 12:40:54 -070082 };
83 };
84
Simon Glass11328532015-08-22 18:31:37 -060085 tpm {
86 reg = <0xfed40000 0x5000>;
87 compatible = "infineon,slb9635lpc";
88 };
89
Simon Glass5f8865f2015-03-02 12:40:54 -070090};