blob: 2f2a349dcdcd9bbf0665bad7031eaabc381f31be [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Vikas Manocha1b51c932016-02-11 15:47:20 -08002/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02003 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha1b51c932016-02-11 15:47:20 -08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Patrice Chotard44d75ac2020-02-03 15:10:40 +010010#include <linux/sizes.h>
11
12/* For booting Linux, use the first 6MB of memory */
13#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
14
Vikas Manocha1b51c932016-02-11 15:47:20 -080015#define CONFIG_SYS_FLASH_BASE 0x08000000
16#define CONFIG_SYS_INIT_SP_ADDR 0x20050000
Vikas Manocha50218ae2017-05-28 12:55:10 -070017
Vikas Manocha1b51c932016-02-11 15:47:20 -080018/*
19 * Configuration of the external SDRAM memory
20 */
Vikas Manocha1b51c932016-02-11 15:47:20 -080021
Vikas Manocha49408022016-03-09 15:18:14 -080022#define CONFIG_SYS_MAX_FLASH_SECT 8
23#define CONFIG_SYS_MAX_FLASH_BANKS 1
Vikas Manocha1b51c932016-02-11 15:47:20 -080024
Michael Kurz812962b2017-01-22 16:04:27 +010025#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
26#define CONFIG_DW_ALTDESCRIPTOR
Michael Kurz812962b2017-01-22 16:04:27 +010027
Vikas Manocha1b51c932016-02-11 15:47:20 -080028#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
29
Vikas Manocha1b51c932016-02-11 15:47:20 -080030#define CONFIG_SYS_CBSIZE 1024
Vikas Manocha1b51c932016-02-11 15:47:20 -080031
Patrice Chotard231902c2019-02-21 10:07:54 +010032#define BOOT_TARGET_DEVICES(func) \
33 func(MMC, mmc, 0)
Vikas Manocha1b51c932016-02-11 15:47:20 -080034
Patrice Chotard231902c2019-02-21 10:07:54 +010035#include <config_distro_bootcmd.h>
36#define CONFIG_EXTRA_ENV_SETTINGS \
37 "kernel_addr_r=0xC0008000\0" \
38 "fdtfile=stm32f746-disco.dtb\0" \
Patrice Chotard0c6aee52020-02-03 15:10:39 +010039 "fdt_addr_r=0xC0408000\0" \
40 "scriptaddr=0xC0418000\0" \
41 "pxefile_addr_r=0xC0428000\0" \
42 "ramdisk_addr_r=0xC0438000\0" \
Patrice Chotard231902c2019-02-21 10:07:54 +010043 BOOTENV
Vikas Manocha1b51c932016-02-11 15:47:20 -080044
Vikas Manocha50218ae2017-05-28 12:55:10 -070045/* For SPL */
46#ifdef CONFIG_SUPPORT_SPL
47#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
Vikas Manocha50218ae2017-05-28 12:55:10 -070048#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
49#define CONFIG_SYS_SPL_LEN 0x00008000
Vikas Manochaf0e32c02017-05-28 12:55:14 -070050#define CONFIG_SYS_UBOOT_START 0x080083FD
Vikas Manocha50218ae2017-05-28 12:55:10 -070051#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
52 CONFIG_SYS_SPL_LEN)
Vikas Manochab785bb42017-05-28 12:55:13 -070053
Vikas Manochab785bb42017-05-28 12:55:13 -070054/* DT blob (fdt) address */
Vikas Manochab785bb42017-05-28 12:55:13 -070055#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
56 0x1C0000)
Vikas Manocha50218ae2017-05-28 12:55:10 -070057#endif
58/* For SPL ends */
59
yannick fertre030af822018-03-02 15:59:28 +010060/* For splashcreen */
yannick fertre030af822018-03-02 15:59:28 +010061
Vikas Manocha1b51c932016-02-11 15:47:20 -080062#endif /* __CONFIG_H */