blob: 29318fad5f0b0cda591db8779af2bbaf34b0ce3b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +08002/*
3 * Copyright 2009 Freescale Semiconductor, Inc.
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +08004 */
5
Scott Woodfac86242012-08-17 19:46:29 -05006#include <asm/processor.h>
7#include <asm/global_data.h>
York Sun37562f62013-10-22 12:39:02 -07008#include <fsl_ifc.h>
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +08009#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060010#include <linux/delay.h>
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080011
Scott Woodfac86242012-08-17 19:46:29 -050012DECLARE_GLOBAL_DATA_PTR;
13
York Sun695c0c32014-04-30 14:43:47 -070014ulong cpu_init_f(void)
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080015{
Tom Rini6a5dccc2022-11-16 13:10:41 -050016#ifdef CFG_SYS_INIT_L2_ADDR
Tom Rinid5c3bf22022-10-28 20:27:12 -040017 ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080018
Tom Rini6a5dccc2022-11-16 13:10:41 -050019 out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080020
21 /* set MBECCDIS=1, SBECCDIS=1 */
22 out_be32(&l2cache->l2errdis,
23 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
24
25 /* set L2E=1 & L2SRAM=001 */
26 out_be32(&l2cache->l2ctl,
27 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080028#endif
York Sun695c0c32014-04-30 14:43:47 -070029
30 return 0;
Scott Woodfac86242012-08-17 19:46:29 -050031}
32
Scott Woodfac86242012-08-17 19:46:29 -050033void udelay(unsigned long usec)
34{
35 u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
36 u32 ticks = ticks_per_usec * usec;
37 u32 s = mfspr(SPRN_TBRL);
38
39 while ((mfspr(SPRN_TBRL) - s) < ticks);
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080040}