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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +08002/*
3 * Copyright 2009 Freescale Semiconductor, Inc.
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +08004 */
5
6#include <common.h>
Scott Woodfac86242012-08-17 19:46:29 -05007#include <asm/processor.h>
8#include <asm/global_data.h>
York Sun37562f62013-10-22 12:39:02 -07009#include <fsl_ifc.h>
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080010#include <asm/io.h>
Simon Glassdbd79542020-05-10 11:40:11 -060011#include <linux/delay.h>
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080012
Scott Woodfac86242012-08-17 19:46:29 -050013DECLARE_GLOBAL_DATA_PTR;
14
York Sun695c0c32014-04-30 14:43:47 -070015ulong cpu_init_f(void)
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080016{
Scott Wood095b7122012-09-20 19:02:18 -050017#ifdef CONFIG_SYS_INIT_L2_ADDR
Tom Rinid5c3bf22022-10-28 20:27:12 -040018 ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080019
20 out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
21
22 /* set MBECCDIS=1, SBECCDIS=1 */
23 out_be32(&l2cache->l2errdis,
24 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
25
26 /* set L2E=1 & L2SRAM=001 */
27 out_be32(&l2cache->l2ctl,
28 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080029#endif
York Sun695c0c32014-04-30 14:43:47 -070030
31 return 0;
Scott Woodfac86242012-08-17 19:46:29 -050032}
33
Scott Woodfac86242012-08-17 19:46:29 -050034void udelay(unsigned long usec)
35{
36 u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
37 u32 ticks = ticks_per_usec * usec;
38 u32 s = mfspr(SPRN_TBRL);
39
40 while ((mfspr(SPRN_TBRL) - s) < ticks);
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080041}