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git01.mediatek.com / filogic / uboot / 87123914ed4131fc0dc86636fa3b68a814126003 / . / test / dm / clk.c
blob: 21997ed892290dc11ed7eb6cb737cfb6aa6b5432 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]2/*
3 * Copyright (C) 2015 Google, Inc
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]4 */
5
6#include <common.h>
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]7#include <clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]8#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]9#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]10#include <malloc.h>
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]11#include <asm/clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]12#include <dm/test.h>
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]13#include <dm/device-internal.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]14#include <linux/err.h>
Simon Glass75c4d412020-07-19 10:15:37 -0600[diff] [blame]15#include <test/test.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]16#include <test/ut.h>
17
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]18/* Base test of the clk uclass */
19static int dm_test_clk_base(struct unit_test_state *uts)
20{
21 struct udevice *dev;
22 struct clk clk_method1;
23 struct clk clk_method2;
24
25 /* Get the device using the clk device */
26 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev));
27
28 /* Get the same clk port in 2 different ways and compare */
29 ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
30 ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
Sekhar Noricf3119d2019-08-01 19:12:55 +0530[diff] [blame]31 ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]32 ut_asserteq(clk_method1.id, clk_method2.id);
33
34 return 0;
35}
36
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]37DM_TEST(dm_test_clk_base, UT_TESTF_SCAN_FDT);
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]38
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]39static int dm_test_clk(struct unit_test_state *uts)
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]40{
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]41 struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]42 ulong rate;
43
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]44 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
45 &dev_fixed));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]46
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]47 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed-factor",
48 &dev_fixed_factor));
49
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]50 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
51 &dev_clk));
52 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
53 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
54 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
55 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]56
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]57 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
58 &dev_test));
59 ut_assertok(sandbox_clk_test_get(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]60 ut_assertok(sandbox_clk_test_devm_get(dev_test));
Fabrice Gasnier11192712018-07-24 16:31:28 +0200[diff] [blame]61 ut_assertok(sandbox_clk_test_valid(dev_test));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]62
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]63 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
64 SANDBOX_CLK_TEST_ID_DEVM_NULL));
65 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
66 SANDBOX_CLK_TEST_ID_DEVM_NULL,
67 0));
68 ut_asserteq(0, sandbox_clk_test_enable(dev_test,
69 SANDBOX_CLK_TEST_ID_DEVM_NULL));
70 ut_asserteq(0, sandbox_clk_test_disable(dev_test,
71 SANDBOX_CLK_TEST_ID_DEVM_NULL));
72
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]73 ut_asserteq(1234,
74 sandbox_clk_test_get_rate(dev_test,
75 SANDBOX_CLK_TEST_ID_FIXED));
76 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
77 SANDBOX_CLK_TEST_ID_SPI));
78 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
79 SANDBOX_CLK_TEST_ID_I2C));
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]80 ut_asserteq(321, sandbox_clk_test_get_rate(dev_test,
81 SANDBOX_CLK_TEST_ID_DEVM1));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]82 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
83 SANDBOX_CLK_TEST_ID_DEVM2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]84
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]85 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED,
86 12345);
87 ut_assert(IS_ERR_VALUE(rate));
88 rate = sandbox_clk_test_get_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED);
89 ut_asserteq(1234, rate);
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]90
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]91 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
92 SANDBOX_CLK_TEST_ID_SPI,
93 1000));
94 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
95 SANDBOX_CLK_TEST_ID_I2C,
96 2000));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]97
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]98 ut_asserteq(1000, sandbox_clk_test_get_rate(dev_test,
99 SANDBOX_CLK_TEST_ID_SPI));
100 ut_asserteq(2000, sandbox_clk_test_get_rate(dev_test,
101 SANDBOX_CLK_TEST_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]102
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]103 ut_asserteq(1000, sandbox_clk_test_set_rate(dev_test,
104 SANDBOX_CLK_TEST_ID_SPI,
105 10000));
106 ut_asserteq(2000, sandbox_clk_test_set_rate(dev_test,
107 SANDBOX_CLK_TEST_ID_I2C,
108 20000));
109
110 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
111 ut_assert(IS_ERR_VALUE(rate));
112 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
113 ut_assert(IS_ERR_VALUE(rate));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]114
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]115 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
116 SANDBOX_CLK_TEST_ID_SPI));
117 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
118 SANDBOX_CLK_TEST_ID_I2C));
119
Dario Binacchib7f85892020-12-30 00:06:31 +0100[diff] [blame]120 ut_asserteq(5000, sandbox_clk_test_round_rate(dev_test,
121 SANDBOX_CLK_TEST_ID_SPI,
122 5000));
123 ut_asserteq(7000, sandbox_clk_test_round_rate(dev_test,
124 SANDBOX_CLK_TEST_ID_I2C,
125 7000));
126
127 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
128 SANDBOX_CLK_TEST_ID_SPI));
129 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
130 SANDBOX_CLK_TEST_ID_I2C));
131
132 rate = sandbox_clk_test_round_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
133 ut_assert(IS_ERR_VALUE(rate));
134 rate = sandbox_clk_test_round_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
135 ut_assert(IS_ERR_VALUE(rate));
136
137 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
138 SANDBOX_CLK_TEST_ID_SPI));
139 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
140 SANDBOX_CLK_TEST_ID_I2C));
141
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]142 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
143 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
144 ut_asserteq(10000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
145 ut_asserteq(20000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
146
147 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_SPI));
148 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
149 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
150
151 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_I2C));
152 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
153 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
154
155 ut_assertok(sandbox_clk_test_disable(dev_test,
156 SANDBOX_CLK_TEST_ID_SPI));
157 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
158 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
159
160 ut_assertok(sandbox_clk_test_disable(dev_test,
161 SANDBOX_CLK_TEST_ID_I2C));
162 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
163 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
164
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]165 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
166 SANDBOX_CLK_ID_SPI));
167 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
168 SANDBOX_CLK_ID_I2C));
169 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
170 SANDBOX_CLK_ID_UART2));
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]171 ut_assertok(sandbox_clk_test_free(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]172 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
173 SANDBOX_CLK_ID_SPI));
174 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
175 SANDBOX_CLK_ID_I2C));
176 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
177 SANDBOX_CLK_ID_UART2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]178
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]179 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
180 SANDBOX_CLK_ID_UART1));
181 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
182 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
183 SANDBOX_CLK_ID_UART1));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]184 return 0;
185}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]186DM_TEST(dm_test_clk, UT_TESTF_SCAN_FDT);
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]187
188static int dm_test_clk_bulk(struct unit_test_state *uts)
189{
190 struct udevice *dev_clk, *dev_test;
191
192 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
193 &dev_clk));
194 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
195 &dev_test));
196 ut_assertok(sandbox_clk_test_get_bulk(dev_test));
197
198 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
199 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
200
201 /* Fixed clock does not support enable, thus should not fail */
202 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
203 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
204 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
205
206 /* Fixed clock does not support disable, thus should not fail */
207 ut_assertok(sandbox_clk_test_disable_bulk(dev_test));
208 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
209 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
210
211 /* Fixed clock does not support enable, thus should not fail */
212 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
213 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
214 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
215
216 /* Fixed clock does not support disable, thus should not fail */
217 ut_assertok(sandbox_clk_test_release_bulk(dev_test));
218 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
219 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]220 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]221
222 return 0;
223}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]224DM_TEST(dm_test_clk_bulk, UT_TESTF_SCAN_FDT);