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git01.mediatek.com / filogic / uboot / 87022a621dbe9dd03cb183ffcc97bc68f0fe28f2 / . / board / renesas / sparrowhawk / sparrowhawk.c
blob: 8e72b5424d15214b2e1fb1a40852a636f345d890 [file] [log] [blame]
Marek Vasut87022a62025-05-31 00:03:40 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
4 */
5
6#include <asm/io.h>
7#include <compiler.h>
8#include <dbsc5.h>
9#include <spl.h>
10
11#if defined(CONFIG_XPL_BUILD)
12
13static const struct renesas_dbsc5_board_config
14renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config = {
15 /* RENESAS V4H Sparrow Hawk (64Gbit 1rank) */
16 .bdcfg_phyvalid = 0xF,
17 .bdcfg_vref_r = 0x0,
18 .bdcfg_vref_w = 0x0,
19 .bdcfg_vref_ca = 0x0,
20 .bdcfg_rfm_chk = true,
21 .ch = {
22 [0] = {
23 .bdcfg_ddr_density = { 0x06, 0xFF },
24 .bdcfg_ca_swap = 0x04506132,
25 .bdcfg_dqs_swap = 0x01,
26 .bdcfg_dq_swap = { 0x26157084, 0x12306854 },
27 .bdcfg_dm_swap = { 0x03, 0x07 },
28 .bdcfg_cs_swap = 0x10
29 },
30 [1] = {
31 .bdcfg_ddr_density = { 0x06, 0xFF },
32 .bdcfg_ca_swap = 0x02431065,
33 .bdcfg_dqs_swap = 0x10,
34 .bdcfg_dq_swap = { 0x56782314, 0x70423856 },
35 .bdcfg_dm_swap = { 0x00, 0x01 },
36 .bdcfg_cs_swap = 0x10
37 },
38 [2] = {
39 .bdcfg_ddr_density = { 0x06, 0xFF },
40 .bdcfg_ca_swap = 0x02150643,
41 .bdcfg_dqs_swap = 0x10,
42 .bdcfg_dq_swap = { 0x58264031, 0x40587236 },
43 .bdcfg_dm_swap = { 0x07, 0x01 },
44 .bdcfg_cs_swap = 0x10
45 },
46 [3] = {
47 .bdcfg_ddr_density = { 0x06, 0xFF },
48 .bdcfg_ca_swap = 0x01546230,
49 .bdcfg_dqs_swap = 0x01,
50 .bdcfg_dq_swap = { 0x45761328, 0x68023745 },
51 .bdcfg_dm_swap = { 0x00, 0x01 },
52 .bdcfg_cs_swap = 0x10
53 }
54 }
55};
56
57static const struct renesas_dbsc5_board_config
58renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config = {
59 /* RENESAS V4H Sparrow Hawk (64Gbit 2rank) */
60 .bdcfg_phyvalid = 0xF,
61 .bdcfg_vref_r = 0x0,
62 .bdcfg_vref_w = 0x0,
63 .bdcfg_vref_ca = 0x0,
64 .bdcfg_rfm_chk = true,
65 .ch = {
66 [0] = {
67 .bdcfg_ddr_density = { 0x06, 0x06 },
68 .bdcfg_ca_swap = 0x04506132,
69 .bdcfg_dqs_swap = 0x01,
70 .bdcfg_dq_swap = { 0x26157084, 0x12306854 },
71 .bdcfg_dm_swap = { 0x03, 0x07 },
72 .bdcfg_cs_swap = 0x10
73 },
74 [1] = {
75 .bdcfg_ddr_density = { 0x06, 0x06 },
76 .bdcfg_ca_swap = 0x02431065,
77 .bdcfg_dqs_swap = 0x10,
78 .bdcfg_dq_swap = { 0x56782314, 0x70423856 },
79 .bdcfg_dm_swap = { 0x00, 0x01 },
80 .bdcfg_cs_swap = 0x10
81 },
82 [2] = {
83 .bdcfg_ddr_density = { 0x06, 0x06 },
84 .bdcfg_ca_swap = 0x02150643,
85 .bdcfg_dqs_swap = 0x10,
86 .bdcfg_dq_swap = { 0x58264031, 0x40587236 },
87 .bdcfg_dm_swap = { 0x07, 0x01 },
88 .bdcfg_cs_swap = 0x10
89 },
90 [3] = {
91 .bdcfg_ddr_density = { 0x06, 0x06 },
92 .bdcfg_ca_swap = 0x01546230,
93 .bdcfg_dqs_swap = 0x01,
94 .bdcfg_dq_swap = { 0x45761328, 0x68023745 },
95 .bdcfg_dm_swap = { 0x00, 0x01 },
96 .bdcfg_cs_swap = 0x10
97 }
98 }
99};
100
101const struct renesas_dbsc5_board_config *
102dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
103{
104 /*
105 * MD[19] is used to discern between 5500 Mbps and 6400 Mbps operation.
106 *
107 * Boards with 1 rank of DRAM can operate at 6400 Mbps, those are the
108 * Sparrow Hawk boards with 8 GiB of DRAM. Boards with 2 ranks of DRAM
109 * are limited to 5500 Mbps operation, those are the boards with 16 GiB
110 * of DRAM.
111 *
112 * Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk
113 * board variants from each other automatically.
114 */
115 if (modemr0 & BIT(19))
116 return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config;
117 else
118 return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config;
119}
120
121#endif
122
123#define RST_MODEMR0 0xe6160000
124
125DECLARE_GLOBAL_DATA_PTR;
126
127void renesas_dram_init_banksize(void)
128{
129 const u32 modemr0 = readl(RST_MODEMR0);
130 int bank;
131
132 /* 8 GiB device, do nothing. */
133 if (!(modemr0 & BIT(19)))
134 return;
135
136 /* 16 GiB device, adjust memory map. */
137 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
138 if (gd->bd->bi_dram[bank].start == 0x480000000ULL)
139 gd->bd->bi_dram[bank].size = 0x180000000ULL;
140 else if (gd->bd->bi_dram[bank].start == 0x600000000ULL)
141 gd->bd->bi_dram[bank].size = 0x200000000ULL;
142 }
143}