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git01.mediatek.com / filogic / uboot / 86a02eeed072532b08a07503da8d9838e87e6154 / . / arch / arm / dts / k3-am642-sk-u-boot.dtsi
blob: 6fcb11bd04d5b78c1edc64b8c78224bab97e2b81 [file] [log] [blame]
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]11 };
12};
13
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]14&main_timer0 {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]15 clock-frequency = <200000000>;
16};
17
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]18&sdhci0 {
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]19 status = "disabled";
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]20};
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]21
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]22&inta_main_dmss {
23 bootph-all;
24};
25
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]26&mdio1_pins_default {
27 bootph-all;
28};
29
30&cpsw3g_mdio {
31 bootph-all;
32};
33
34&cpsw3g_phy0 {
35 bootph-all;
36};
37
38&cpsw3g_phy1 {
39 bootph-all;
40};
41
42&rgmii1_pins_default {
43 bootph-all;
44};
45
46&rgmii2_pins_default {
47 bootph-all;
48};
49
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]50&cpsw3g {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]51 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]52
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]53 ethernet-ports {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]54 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]55 };
56};
57
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]58&phy_gmii_sel {
59 bootph-all;
60};
61
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]62&cpsw_port2 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]63 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]64};
65
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]66&main_bcdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]67 reg = <0x00 0x485c0100 0x00 0x100>,
68 <0x00 0x4c000000 0x00 0x20000>,
69 <0x00 0x4a820000 0x00 0x20000>,
70 <0x00 0x4aa40000 0x00 0x20000>,
71 <0x00 0x4bc00000 0x00 0x100000>,
72 <0x00 0x48600000 0x00 0x8000>,
73 <0x00 0x484a4000 0x00 0x2000>,
74 <0x00 0x484c2000 0x00 0x2000>;
75 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
76 "cfg", "tchan", "rchan";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]77 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]78};
79
80&main_pktdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]81 reg = <0x00 0x485c0000 0x00 0x100>,
82 <0x00 0x4a800000 0x00 0x20000>,
83 <0x00 0x4aa00000 0x00 0x40000>,
84 <0x00 0x4b800000 0x00 0x400000>,
85 <0x00 0x485e0000 0x00 0x20000>,
86 <0x00 0x484a0000 0x00 0x4000>,
87 <0x00 0x484c0000 0x00 0x2000>,
88 <0x00 0x48430000 0x00 0x4000>;
89 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
90 "tchan", "rchan", "rflow";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]91 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]92};
93
94&rgmii1_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]95 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]96};
97
98&rgmii2_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]99 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]100};
101
102&mdio1_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]103 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]104};
105
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]106&cpsw3g_phy1 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]107 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]108};
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]109
Roger Quadros672caea2024-01-31 15:33:48 +0200[diff] [blame]110&serdes_ln_ctrl {
111 bootph-all;
112};
113
Jonathan Humphreyse1ce4f42024-02-23 18:17:02 -0600[diff] [blame]114&ospi0_pins_default {
115 bootph-all;
116};
117
118&fss {
119 bootph-all;
120};
121
122&ospi0 {
123 bootph-all;
124
125 flash@0 {
126 bootph-all;
127 };
128};