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git01.mediatek.com / filogic / uboot / 8656583fcf777befffb29d3191a446ec22fe4bf0 / . / board / nvidia / harmony / harmony.c
blob: c892a25751f9719ee8fe9740c11405d3c9d67ec3 [file] [log] [blame]
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]1/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]6 */
7
8#include <common.h>
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]9#include <lcd.h>
Tom Warrene1495582011-04-14 12:09:41 +0000[diff] [blame]10#include <asm/io.h>
Simon Glassd677c8e2012-01-11 12:42:27 +0000[diff] [blame]11#include <asm/arch/clock.h>
12#include <asm/arch/funcmux.h>
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]13#include <asm/arch/pinmux.h>
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]14#include <asm/arch/tegra.h>
Stephen Warrenfba87542011-10-31 06:51:36 +0000[diff] [blame]15#include <asm/gpio.h>
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]16
Tom Warren8c57e962012-05-22 11:44:48 +0000[diff] [blame]17#ifdef CONFIG_TEGRA_MMC
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]18/*
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]19 * Routine: pin_mux_mmc
20 * Description: setup the pin muxes/tristate values for the SDMMC(s)
21 */
Tom Warren9745cf82013-02-21 12:31:30 +0000[diff] [blame]22void pin_mux_mmc(void)
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]23{
Simon Glassd677c8e2012-01-11 12:42:27 +0000[diff] [blame]24 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
25 funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]26
27 /* For power GPIO PI6 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]28 pinmux_tristate_disable(PMUX_PINGRP_ATA);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]29 /* For CD GPIO PH2 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]30 pinmux_tristate_disable(PMUX_PINGRP_ATD);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]31
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]32 /* For power GPIO PT3 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]33 pinmux_tristate_disable(PMUX_PINGRP_DTB);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]34 /* For CD GPIO PI5 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]35 pinmux_tristate_disable(PMUX_PINGRP_ATC);
Stephen Warrenf8eac0d2011-10-31 06:51:35 +0000[diff] [blame]36}
Tom Warren97bf58f2011-09-21 12:40:07 +0000[diff] [blame]37#endif
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]38
39void pin_mux_usb(void)
40{
41 funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]42 pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
43 pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]44 /* USB2 PHY reset GPIO */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]45 pinmux_tristate_disable(PMUX_PINGRP_UAC);
Stephen Warrenb03192e2012-10-12 09:45:48 +0000[diff] [blame]46}
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]47
48void pin_mux_display(void)
49{
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]50 pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
51 pinmux_tristate_disable(PMUX_PINGRP_SDC);
Stephen Warrenf0083342013-06-18 09:46:51 -0600[diff] [blame]52}