Blame - arch/arc/Kconfig - filogic/uboot

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Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	1	menu "ARC architecture"
				2	depends on ARC
				3
				4	config SYS_ARCH
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	5	default "arc"
				6
Alexey Brodkin	93206d2	2015-02-03 13:58:20 +0300	[diff] [blame]	7	config USE_PRIVATE_LIBGCC
				8	default y
				9
Alexey Brodkin	7739f9f	2014-12-25 18:47:45 +0300	[diff] [blame]	10	config SYS_CPU
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	11	default "arcv1" if ISA_ARCOMPACT
				12	default "arcv2" if ISA_ARCV2
Alexey Brodkin	7739f9f	2014-12-25 18:47:45 +0300	[diff] [blame]	13
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	14	choice
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	15	prompt "ARC Instruction Set"
				16	default ISA_ARCOMPACT
				17
				18	config ISA_ARCOMPACT
				19	bool "ARCompact ISA"
				20	help
				21	The original ARC ISA of ARC600/700 cores
				22
				23	config ISA_ARCV2
				24	bool "ARC ISA v2"
				25	help
				26	ISA for the Next Generation ARC-HS cores
				27
				28	endchoice
				29
				30	choice
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	31	prompt "CPU selection"
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	32	default CPU_ARC770D if ISA_ARCOMPACT
				33	default CPU_ARCHS38 if ISA_ARCV2
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	34
				35	config CPU_ARC750D
				36	bool "ARC 750D"
				37	select ARC_MMU_V2
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	38	depends on ISA_ARCOMPACT
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	39	help
				40	Choose this option to build an U-Boot for ARC750D CPU.
				41
				42	config CPU_ARC770D
				43	bool "ARC 770D"
				44	select ARC_MMU_V3
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	45	depends on ISA_ARCOMPACT
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	46	help
				47	Choose this option to build an U-Boot for ARC770D CPU.
				48
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	49	config CPU_ARCEM6
				50	bool "ARC EM6"
				51	select ARC_MMU_ABSENT
				52	depends on ISA_ARCV2
				53	help
				54	Next Generation ARC Core based on ISA-v2 ISA without MMU.
				55
				56	config CPU_ARCHS36
				57	bool "ARC HS36"
				58	select ARC_MMU_ABSENT
				59	depends on ISA_ARCV2
				60	help
				61	Next Generation ARC Core based on ISA-v2 ISA without MMU.
				62
				63	config CPU_ARCHS38
				64	bool "ARC HS38"
				65	select ARC_MMU_V4
				66	depends on ISA_ARCV2
				67	help
				68	Next Generation ARC Core based on ISA-v2 ISA with MMU.
				69
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	70	endchoice
				71
				72	choice
				73	prompt "MMU Version"
				74	default ARC_MMU_V3 if CPU_ARC770D
				75	default ARC_MMU_V2 if CPU_ARC750D
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	76	default ARC_MMU_ABSENT if CPU_ARCEM6
				77	default ARC_MMU_ABSENT if CPU_ARCHS36
				78	default ARC_MMU_V4 if CPU_ARCHS38
				79
				80	config ARC_MMU_ABSENT
				81	bool "No MMU"
				82	help
				83	No MMU
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	84
				85	config ARC_MMU_V2
				86	bool "MMU v2"
				87	depends on CPU_ARC750D
				88	help
				89	Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
				90	when 2 D-TLB and 1 I-TLB entries index into same 2way set.
				91
				92	config ARC_MMU_V3
				93	bool "MMU v3"
				94	depends on CPU_ARC770D
				95	help
				96	Introduced with ARC700 4.10: New Features
				97	Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
				98	Shared Address Spaces (SASID)
				99
Alexey Brodkin	e41a3d5	2015-01-13 18:35:46 +0300	[diff] [blame]	100	config ARC_MMU_V4
				101	bool "MMU v4"
				102	depends on CPU_ARCHS38
				103	help
				104	Introduced as a part of ARC HS38 release.
				105
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	106	endchoice
				107
Alexey Brodkin	cbd76c3	2015-02-03 13:58:14 +0300	[diff] [blame]	108	config CPU_BIG_ENDIAN
				109	bool "Enable Big Endian Mode"
				110	default n
				111	help
				112	Build kernel for Big Endian Mode of ARC CPU
				113
Alexey Brodkin	6b95cca	2015-02-03 13:58:13 +0300	[diff] [blame]	114	config SYS_ICACHE_OFF
				115	bool "Do not use Instruction Cache"
				116	default n
				117
				118	config SYS_DCACHE_OFF
				119	bool "Do not use Data Cache"
				120	default n
				121
				122	config ARC_CACHE_LINE_SHIFT
				123	int "Cache Line Length (as power of 2)"
				124	range 5 7
				125	default "6"
				126	depends on !SYS_DCACHE_OFF \|\| !SYS_DCACHE_OFF
				127	help
				128	Starting with ARC700 4.9, Cache line length is configurable,
				129	This option specifies "N", with Line-len = 2 power N
				130	So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
				131	Linux only supports same line lengths for I and D caches.
				132
Alexey Brodkin	f431e26	2015-02-03 13:58:11 +0300	[diff] [blame]	133	choice
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	134	prompt "Target select"
				135
				136	config TARGET_TB100
				137	bool "Support tb100"
				138
				139	config TARGET_ARCANGEL4
				140	bool "Support arcangel4"
				141
Masahiro Yamada	d3ae678	2014-07-30 14:08:14 +0900	[diff] [blame]	142	config TARGET_AXS101
				143	bool "Support axs101"
				144
				145	endchoice
				146
				147	source "board/abilis/tb100/Kconfig"
				148	source "board/synopsys/Kconfig"
				149	source "board/synopsys/axs101/Kconfig"
				150
				151	endmenu