| Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | menu "ARC architecture" |
| 2 | depends on ARC |
| 3 | |
| 4 | config SYS_ARCH |
| Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 5 | default "arc" |
| 6 | |
| Alexey Brodkin | 93206d2 | 2015-02-03 13:58:20 +0300 | [diff] [blame^] | 7 | config USE_PRIVATE_LIBGCC |
| 8 | default y |
| 9 | |
| Alexey Brodkin | 7739f9f | 2014-12-25 18:47:45 +0300 | [diff] [blame] | 10 | config SYS_CPU |
| Alexey Brodkin | 167bfbc | 2014-12-25 18:54:58 +0300 | [diff] [blame] | 11 | default "arcv1" |
| Alexey Brodkin | 7739f9f | 2014-12-25 18:47:45 +0300 | [diff] [blame] | 12 | |
| Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 13 | choice |
| Alexey Brodkin | f431e26 | 2015-02-03 13:58:11 +0300 | [diff] [blame] | 14 | prompt "CPU selection" |
| 15 | default CPU_ARC770D |
| 16 | |
| 17 | config CPU_ARC750D |
| 18 | bool "ARC 750D" |
| 19 | select ARC_MMU_V2 |
| 20 | help |
| 21 | Choose this option to build an U-Boot for ARC750D CPU. |
| 22 | |
| 23 | config CPU_ARC770D |
| 24 | bool "ARC 770D" |
| 25 | select ARC_MMU_V3 |
| 26 | help |
| 27 | Choose this option to build an U-Boot for ARC770D CPU. |
| 28 | |
| 29 | endchoice |
| 30 | |
| 31 | choice |
| 32 | prompt "MMU Version" |
| 33 | default ARC_MMU_V3 if CPU_ARC770D |
| 34 | default ARC_MMU_V2 if CPU_ARC750D |
| 35 | |
| 36 | config ARC_MMU_V2 |
| 37 | bool "MMU v2" |
| 38 | depends on CPU_ARC750D |
| 39 | help |
| 40 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio |
| 41 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. |
| 42 | |
| 43 | config ARC_MMU_V3 |
| 44 | bool "MMU v3" |
| 45 | depends on CPU_ARC770D |
| 46 | help |
| 47 | Introduced with ARC700 4.10: New Features |
| 48 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) |
| 49 | Shared Address Spaces (SASID) |
| 50 | |
| 51 | endchoice |
| 52 | |
| Alexey Brodkin | cbd76c3 | 2015-02-03 13:58:14 +0300 | [diff] [blame] | 53 | config CPU_BIG_ENDIAN |
| 54 | bool "Enable Big Endian Mode" |
| 55 | default n |
| 56 | help |
| 57 | Build kernel for Big Endian Mode of ARC CPU |
| 58 | |
| Alexey Brodkin | 6b95cca | 2015-02-03 13:58:13 +0300 | [diff] [blame] | 59 | config SYS_ICACHE_OFF |
| 60 | bool "Do not use Instruction Cache" |
| 61 | default n |
| 62 | |
| 63 | config SYS_DCACHE_OFF |
| 64 | bool "Do not use Data Cache" |
| 65 | default n |
| 66 | |
| 67 | config ARC_CACHE_LINE_SHIFT |
| 68 | int "Cache Line Length (as power of 2)" |
| 69 | range 5 7 |
| 70 | default "6" |
| 71 | depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF |
| 72 | help |
| 73 | Starting with ARC700 4.9, Cache line length is configurable, |
| 74 | This option specifies "N", with Line-len = 2 power N |
| 75 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively |
| 76 | Linux only supports same line lengths for I and D caches. |
| 77 | |
| Alexey Brodkin | f431e26 | 2015-02-03 13:58:11 +0300 | [diff] [blame] | 78 | choice |
| Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 79 | prompt "Target select" |
| 80 | |
| 81 | config TARGET_TB100 |
| 82 | bool "Support tb100" |
| 83 | |
| 84 | config TARGET_ARCANGEL4 |
| 85 | bool "Support arcangel4" |
| 86 | |
| Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 87 | config TARGET_AXS101 |
| 88 | bool "Support axs101" |
| 89 | |
| 90 | endchoice |
| 91 | |
| 92 | source "board/abilis/tb100/Kconfig" |
| 93 | source "board/synopsys/Kconfig" |
| 94 | source "board/synopsys/axs101/Kconfig" |
| 95 | |
| 96 | endmenu |