blob: ec9a0a01610497108018d0c30c2f63b8784571a4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekc8cf4712014-02-05 08:06:29 +01002/*
3 * Copyright (c) 2004-2008 Texas Instruments
4 *
5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Michal Simekc8cf4712014-02-05 08:06:29 +01007 */
8
9OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
10OUTPUT_ARCH(arm)
11ENTRY(_start)
12SECTIONS
13{
14 . = 0x00000000;
15
16 . = ALIGN(4);
17 .text :
18 {
19 *(.__image_copy_start)
Masahiro Yamada22ea4152014-06-05 19:47:45 +090020 *(.vectors)
Michal Simekc8cf4712014-02-05 08:06:29 +010021 CPUDIR/start.o (.text*)
22 *(.text*)
23 }
24
25 . = ALIGN(4);
26 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
27
28 . = ALIGN(4);
29 .data : {
30 *(.data*)
31 }
32
33 . = ALIGN(4);
34
35 . = .;
36
37 . = ALIGN(4);
38 .u_boot_list : {
39 KEEP(*(SORT(.u_boot_list*)));
40 }
41
42 . = ALIGN(4);
43
Alexander Grafa56b5f12017-07-03 13:41:34 +020044 .__efi_runtime_start : {
45 *(.__efi_runtime_start)
46 }
47
48 .efi_runtime : {
49 *(efi_runtime_text)
50 *(efi_runtime_data)
51 }
52
53 .__efi_runtime_stop : {
54 *(.__efi_runtime_stop)
55 }
56
57 .efi_runtime_rel_start :
58 {
59 *(.__efi_runtime_rel_start)
60 }
61
62 .efi_runtime_rel : {
63 *(.relefi_runtime_text)
64 *(.relefi_runtime_data)
65 }
66
67 .efi_runtime_rel_stop :
68 {
69 *(.__efi_runtime_rel_stop)
70 }
71
72 . = ALIGN(4);
Michal Simekc8cf4712014-02-05 08:06:29 +010073 .image_copy_end :
74 {
75 *(.__image_copy_end)
76 }
77
78 .rel_dyn_start :
79 {
80 *(.__rel_dyn_start)
81 }
82
83 .rel.dyn : {
84 *(.rel*)
85 }
86
87 .rel_dyn_end :
88 {
89 *(.__rel_dyn_end)
90 }
91
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010092 .end :
93 {
94 *(.__end)
95 }
96
97 _image_binary_end = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010098
99/*
100 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
101 * __bss_base and __bss_limit are for linker only (overlay ordering)
102 */
103
104 .bss_start __rel_dyn_start (OVERLAY) : {
105 KEEP(*(.__bss_start));
106 __bss_base = .;
107 }
108
109 .bss __bss_base (OVERLAY) : {
110 *(.bss*)
111 . = ALIGN(4);
112 __bss_limit = .;
113 }
114
115 .bss_end __bss_limit (OVERLAY) : {
116 KEEP(*(.__bss_end));
117 }
118
119 /*
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200120 * Zynq needs to discard these sections because the user
Michal Simekc8cf4712014-02-05 08:06:29 +0100121 * is expected to pass this image on to tools for boot.bin
122 * generation that require them to be dropped.
123 */
124 /DISCARD/ : { *(.dynsym) }
125 /DISCARD/ : { *(.dynbss*) }
126 /DISCARD/ : { *(.dynstr*) }
127 /DISCARD/ : { *(.dynamic*) }
128 /DISCARD/ : { *(.plt*) }
129 /DISCARD/ : { *(.interp*) }
130 /DISCARD/ : { *(.gnu*) }
131 /DISCARD/ : { *(.ARM.exidx*) }
132 /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
133}