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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha33542982014-04-08 19:13:44 +05302/* Copyright 2013 Freescale Semiconductor, Inc.
Prabhakar Kushwaha33542982014-04-08 19:13:44 +05303 */
4
5#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07006#include <clock_legacy.h>
Simon Glassa73bda42015-11-08 23:47:45 -07007#include <console.h>
Simon Glass79fd2142019-08-01 09:46:43 -06008#include <env.h>
Simon Glass9d1f6192019-08-02 09:44:25 -06009#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -070010#include <init.h>
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053011#include <asm/spl.h>
12#include <malloc.h>
13#include <ns16550.h>
14#include <nand.h>
15#include <i2c.h>
16#include "../common/qixis.h"
17#include "b4860qds_qixis.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
21phys_size_t get_effective_memsize(void)
22{
23 return CONFIG_SYS_L3_SIZE;
24}
25
26unsigned long get_board_sys_clk(void)
27{
28 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
29
30 switch ((sysclk_conf & 0x0C) >> 2) {
31 case QIXIS_CLK_100:
32 return 100000000;
33 case QIXIS_CLK_125:
34 return 125000000;
35 case QIXIS_CLK_133:
36 return 133333333;
37 }
38 return 66666666;
39}
40
41unsigned long get_board_ddr_clk(void)
42{
43 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
44
45 switch (ddrclk_conf & 0x03) {
46 case QIXIS_CLK_100:
47 return 100000000;
48 case QIXIS_CLK_125:
49 return 125000000;
50 case QIXIS_CLK_133:
51 return 133333333;
52 }
53 return 66666666;
54}
55
56void board_init_f(ulong bootflag)
57{
58 u32 plat_ratio, sys_clk, uart_clk;
59 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
60
61 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
62 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
63
64 /* Update GD pointer */
65 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
66
67 /* compiler optimization barrier needed for GCC >= 3.4 */
68 __asm__ __volatile__("" : : : "memory");
69
70 console_init_f();
71
72 /* initialize selected port with appropriate baud rate */
73 sys_clk = get_board_sys_clk();
74 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
75 uart_clk = sys_clk * plat_ratio / 2;
76
77 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
78 uart_clk / 16 / CONFIG_BAUDRATE);
79
80 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
81}
82
83void board_init_r(gd_t *gd, ulong dest_addr)
84{
85 bd_t *bd;
86
87 bd = (bd_t *)(gd + sizeof(gd_t));
88 memset(bd, 0, sizeof(bd_t));
89 gd->bd = bd;
90 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
91 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
92
Simon Glass302445a2017-01-23 13:31:22 -070093 arch_cpu_init();
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053094 get_clocks();
95 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
96 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040097 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053098
99#ifndef CONFIG_SPL_NAND_BOOT
100 env_init();
101 env_relocate();
102#else
103 /* relocate environment function pointers etc. */
104 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500105 (uchar *)SPL_ENV_ADDR);
106 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -0600107 gd->env_valid = ENV_VALID;
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530108#endif
109
110 i2c_init_all();
111
112 puts("\n\n");
113
Simon Glassd35f3382017-04-06 12:47:05 -0600114 dram_init();
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530115
116#ifdef CONFIG_SPL_NAND_BOOT
117 nand_boot();
118#endif
119}