blob: a16db9d59a3291596433855111fb97953d4cdd3b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha33542982014-04-08 19:13:44 +05302/* Copyright 2013 Freescale Semiconductor, Inc.
Prabhakar Kushwaha33542982014-04-08 19:13:44 +05303 */
4
5#include <common.h>
Simon Glassa73bda42015-11-08 23:47:45 -07006#include <console.h>
Simon Glass79fd2142019-08-01 09:46:43 -06007#include <env.h>
Simon Glass9d1f6192019-08-02 09:44:25 -06008#include <env_internal.h>
Simon Glass284f71b2019-12-28 10:44:45 -07009#include <init.h>
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053010#include <asm/spl.h>
11#include <malloc.h>
12#include <ns16550.h>
13#include <nand.h>
14#include <i2c.h>
15#include "../common/qixis.h"
16#include "b4860qds_qixis.h"
17
18DECLARE_GLOBAL_DATA_PTR;
19
20phys_size_t get_effective_memsize(void)
21{
22 return CONFIG_SYS_L3_SIZE;
23}
24
25unsigned long get_board_sys_clk(void)
26{
27 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
28
29 switch ((sysclk_conf & 0x0C) >> 2) {
30 case QIXIS_CLK_100:
31 return 100000000;
32 case QIXIS_CLK_125:
33 return 125000000;
34 case QIXIS_CLK_133:
35 return 133333333;
36 }
37 return 66666666;
38}
39
40unsigned long get_board_ddr_clk(void)
41{
42 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
43
44 switch (ddrclk_conf & 0x03) {
45 case QIXIS_CLK_100:
46 return 100000000;
47 case QIXIS_CLK_125:
48 return 125000000;
49 case QIXIS_CLK_133:
50 return 133333333;
51 }
52 return 66666666;
53}
54
55void board_init_f(ulong bootflag)
56{
57 u32 plat_ratio, sys_clk, uart_clk;
58 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
59
60 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
61 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
62
63 /* Update GD pointer */
64 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
65
66 /* compiler optimization barrier needed for GCC >= 3.4 */
67 __asm__ __volatile__("" : : : "memory");
68
69 console_init_f();
70
71 /* initialize selected port with appropriate baud rate */
72 sys_clk = get_board_sys_clk();
73 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
74 uart_clk = sys_clk * plat_ratio / 2;
75
76 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
77 uart_clk / 16 / CONFIG_BAUDRATE);
78
79 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
80}
81
82void board_init_r(gd_t *gd, ulong dest_addr)
83{
84 bd_t *bd;
85
86 bd = (bd_t *)(gd + sizeof(gd_t));
87 memset(bd, 0, sizeof(bd_t));
88 gd->bd = bd;
89 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
90 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
91
Simon Glass302445a2017-01-23 13:31:22 -070092 arch_cpu_init();
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053093 get_clocks();
94 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
95 CONFIG_SPL_RELOC_MALLOC_SIZE);
Sumit Garg2ff056b2016-05-25 12:41:48 -040096 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
Prabhakar Kushwaha33542982014-04-08 19:13:44 +053097
98#ifndef CONFIG_SPL_NAND_BOOT
99 env_init();
100 env_relocate();
101#else
102 /* relocate environment function pointers etc. */
103 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
Tom Rini5cd7ece2019-11-18 20:02:10 -0500104 (uchar *)SPL_ENV_ADDR);
105 gd->env_addr = (ulong)(SPL_ENV_ADDR);
Simon Glass4bc2ad22017-08-03 12:21:56 -0600106 gd->env_valid = ENV_VALID;
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530107#endif
108
109 i2c_init_all();
110
111 puts("\n\n");
112
Simon Glassd35f3382017-04-06 12:47:05 -0600113 dram_init();
Prabhakar Kushwaha33542982014-04-08 19:13:44 +0530114
115#ifdef CONFIG_SPL_NAND_BOOT
116 nand_boot();
117#endif
118}